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Show patches with
: Submitter =
Richard Henderson
| Archived =
No
| 22275 patches
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Submitter
State
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Delegate
------
Nobody
andy.doan@linaro.org
andy.doan@linaro.org
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«
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Patch
Series
S/W/F
Date
Submitter
Delegate
State
gitlab: Update msys2-64bit runner tags
gitlab: Update msys2-64bit runner tags
-
-
-
2024-05-07
Richard Henderson
Accepted
[PULL,9/9] gitlab: Streamline ubuntu-22.04-s390x
[PULL,1/9] tcg: Add write_aofs to GVecGen3i
-
-
-
2024-05-07
Richard Henderson
Accepted
[PULL,8/9] gitlab: Drop --static from s390x linux-user build
[PULL,1/9] tcg: Add write_aofs to GVecGen3i
-
-
-
2024-05-07
Richard Henderson
Accepted
[PULL,7/9] gitlab: Drop --disable-libssh from ubuntu-22.04-s390x.yml
[PULL,1/9] tcg: Add write_aofs to GVecGen3i
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-
-
2024-05-07
Richard Henderson
Accepted
[PULL,6/9] target/sh4: Update DisasContextBase.insn_start
[PULL,1/9] tcg: Add write_aofs to GVecGen3i
-
-
-
2024-05-07
Richard Henderson
Accepted
[PULL,5/9] accel/tcg: Introduce CF_BP_PAGE
[PULL,1/9] tcg: Add write_aofs to GVecGen3i
-
-
-
2024-05-07
Richard Henderson
New
[PULL,4/9] tcg/optimize: Optimize setcond with zmask
[PULL,1/9] tcg: Add write_aofs to GVecGen3i
-
-
-
2024-05-07
Richard Henderson
Accepted
[PULL,3/9] tcg/i386: Optimize setcond of TST{EQ,NE} with 0xffffffff
[PULL,1/9] tcg: Add write_aofs to GVecGen3i
-
-
-
2024-05-07
Richard Henderson
Accepted
[PULL,2/9] tcg/i386: Simplify immediate 8-bit logical vector shifts
[PULL,1/9] tcg: Add write_aofs to GVecGen3i
-
-
-
2024-05-07
Richard Henderson
Accepted
[PULL,1/9] tcg: Add write_aofs to GVecGen3i
[PULL,1/9] tcg: Add write_aofs to GVecGen3i
-
-
-
2024-05-07
Richard Henderson
Accepted
[PULL,0/9] tcg + misc patch queue
-
-
-
2024-05-07
Richard Henderson
New
gitlab: Rename ubuntu-22.04-s390x-all to *-system
gitlab: Rename ubuntu-22.04-s390x-all to *-system
-
-
-
2024-05-06
Richard Henderson
New
gitlab: Drop --static from s390x linux-user build
gitlab: Drop --static from s390x linux-user build
-
-
-
2024-05-06
Richard Henderson
Superseded
target/sh4: Update DisasContextBase.insn_start
target/sh4: Update DisasContextBase.insn_start
-
-
-
2024-05-06
Richard Henderson
Superseded
[57/57] target/arm: Convert SQDMULH, SQRDMULH to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[56/57] target/arm: Tidy SQDMULH, SQRDMULH (vector)
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[55/57] target/arm: Convert MLA, MLS to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[54/57] target/arm: Convert MUL, PMUL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[53/57] target/arm: Convert SABA, SABD, UABA, UABD to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[52/57] target/arm: Convert SMAX, SMIN, UMAX, UMIN to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[51/57] target/arm: Convert SRHADD, URHADD to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[50/57] target/arm: Convert SRHADD, URHADD to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[49/57] target/arm: Convert SHSUB, UHSUB to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[48/57] target/arm: Convert SHSUB, UHSUB to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[47/57] target/arm: Convert SHADD, UHADD to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[46/57] target/arm: Convert SHADD, UHADD to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[45/57] target/arm: Use TCG_COND_TSTNE in gen_cmtst_{i32,i64}
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[44/57] target/arm: Convert CMGT, CMHI, CMGE, CMHS, CMTST, CMEQ to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[43/57] target/arm: Convert ADD, SUB (vector) to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[42/57] target/arm: Convert SQRSHL, UQRSHL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[41/57] target/arm: Convert SQRSHL and UQRSHL (register) to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[40/57] target/arm: Convert SQSHL, UQSHL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[39/57] target/arm: Convert SQSHL and UQSHL (register) to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[38/57] target/arm: Convert SRSHL, URSHL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[37/57] target/arm: Convert SRSHL and URSHL (register) to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[36/57] target/arm: Convert SSHL, USHL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[35/57] target/arm: Convert SUQADD, USQADD to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[34/57] target/arm: Convert SQADD, SQSUB, UQADD, UQSUB to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[33/57] target/arm: Inline scalar SQADD, UQADD, SQSUB, UQSUB
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[32/57] target/arm: Inline scalar SUQADD and USQADD
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[31/57] target/arm: Convert SUQADD and USQADD to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[30/57] target/arm: Improve vector UQADD, UQSUB, SQADD, SQSUB
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[29/57] target/arm: Convert disas_simd_3same_logic to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[28/57] target/arm: Convert FMLAL, FMLSL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[27/57] target/arm: Use gvec for neon pmax, pmin
target/arm: Convert a64 advsimd to decodetree (part 1)
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-
-
2024-05-06
Richard Henderson
New
[26/57] target/arm: Convert SMAXP, SMINP, UMAXP, UMINP to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[25/57] target/arm: Use gvec for neon padd
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[24/57] target/arm: Convert ADDP to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[23/57] target/arm: Use gvec for neon faddp, fmaxp, fminp
target/arm: Convert a64 advsimd to decodetree (part 1)
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-
-
2024-05-06
Richard Henderson
New
[22/57] target/arm: Convert FMAXP, FMINP, FMAXNMP, FMINNMP to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
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-
2024-05-06
Richard Henderson
New
[21/57] target/arm: Convert FADDP to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
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-
-
2024-05-06
Richard Henderson
New
[20/57] target/arm: Convert FRECPS, FRSQRTS to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[19/57] target/arm: Convert FABD to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[18/57] target/arm: Convert FCMEQ, FCMGE, FCMGT, FACGE, FACGT to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
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-
-
2024-05-06
Richard Henderson
New
[17/57] target/arm: Convert FMLA, FMLS to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
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-
-
2024-05-06
Richard Henderson
New
[16/57] target/arm: Convert FNMUL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
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-
-
2024-05-06
Richard Henderson
New
[15/57] target/arm: Expand vfp neg and abs inline
target/arm: Convert a64 advsimd to decodetree (part 1)
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-
-
2024-05-06
Richard Henderson
New
[14/57] target/arm: Convert FMAX, FMIN, FMAXNM, FMINNM to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[13/57] target/arm: Convert FADD, FSUB, FDIV, FMUL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[12/57] target/arm: Convert FMULX to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
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-
-
2024-05-06
Richard Henderson
New
[11/57] target/arm: Convert Advanced SIMD copy to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[10/57] target/arm: Convert XAR to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[09/57] target/arm: Convert Cryptographic 3-register, imm2 to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[08/57] target/arm: Convert Cryptographic 4-register to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[07/57] target/arm: Convert Cryptographic 2-register SHA512 to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[06/57] target/arm: Convert Cryptographic 3-register SHA512 to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[05/57] target/arm: Convert Cryptographic 2-register SHA to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[04/57] target/arm: Convert Cryptographic 3-register SHA to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[03/57] target/arm: Convert Cryptographic AES to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[02/57] target/arm: Split out gengvec64.c
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[01/57] target/arm: Split out gengvec.c
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-06
Richard Henderson
New
[PULL,9/9] target/alpha: Implement CF_PCREL
[PULL,1/9] target/alpha: Use cpu_env in preference to ALPHA_CPU
-
-
-
2024-05-04
Richard Henderson
Accepted
[PULL,8/9] target/alpha: Split out gen_pc_disp
[PULL,1/9] target/alpha: Use cpu_env in preference to ALPHA_CPU
-
-
-
2024-05-04
Richard Henderson
Accepted
[PULL,7/9] target/alpha: Split out gen_goto_tb
[PULL,1/9] target/alpha: Use cpu_env in preference to ALPHA_CPU
-
-
-
2024-05-04
Richard Henderson
Accepted
[PULL,6/9] target/alpha: Simplify gen_bcond_internal()
[PULL,1/9] target/alpha: Use cpu_env in preference to ALPHA_CPU
-
-
-
2024-05-04
Richard Henderson
Accepted
[PULL,5/9] target/alpha: Return DISAS_NORETURN once
[PULL,1/9] target/alpha: Use cpu_env in preference to ALPHA_CPU
-
-
-
2024-05-04
Richard Henderson
Accepted
[PULL,4/9] target/alpha: Inline DISAS_PC_UPDATED and return DISAS_NORETURN
[PULL,1/9] target/alpha: Use cpu_env in preference to ALPHA_CPU
-
-
-
2024-05-04
Richard Henderson
Accepted
[PULL,3/9] target/alpha: Use DISAS_NEXT definition instead of magic '0' value
[PULL,1/9] target/alpha: Use cpu_env in preference to ALPHA_CPU
-
-
-
2024-05-04
Richard Henderson
New
[PULL,2/9] target/alpha: Hoist branch shift to initial decode
[PULL,1/9] target/alpha: Use cpu_env in preference to ALPHA_CPU
-
-
-
2024-05-04
Richard Henderson
Accepted
[PULL,1/9] target/alpha: Use cpu_env in preference to ALPHA_CPU
[PULL,1/9] target/alpha: Use cpu_env in preference to ALPHA_CPU
-
-
-
2024-05-04
Richard Henderson
Accepted
[PULL,0/9] target/alpha: Implement CF_PCREL
-
-
-
2024-05-04
Richard Henderson
New
[PULL,10/10] tests/bench: Add bufferiszero-bench
[PULL,01/10] util/bufferiszero: Remove SSE4.1 variant
-
-
-
2024-05-03
Richard Henderson
Accepted
[PULL,09/10] util/bufferiszero: Add simd acceleration for aarch64
[PULL,01/10] util/bufferiszero: Remove SSE4.1 variant
-
-
-
2024-05-03
Richard Henderson
Accepted
[PULL,08/10] util/bufferiszero: Simplify test_buffer_is_zero_next_accel
[PULL,01/10] util/bufferiszero: Remove SSE4.1 variant
-
-
-
2024-05-03
Richard Henderson
New
[PULL,07/10] util/bufferiszero: Introduce biz_accel_fn typedef
[PULL,01/10] util/bufferiszero: Remove SSE4.1 variant
-
-
-
2024-05-03
Richard Henderson
Accepted
[PULL,06/10] util/bufferiszero: Improve scalar variant
[PULL,01/10] util/bufferiszero: Remove SSE4.1 variant
-
-
-
2024-05-03
Richard Henderson
New
[PULL,05/10] util/bufferiszero: Optimize SSE2 and AVX2 variants
[PULL,01/10] util/bufferiszero: Remove SSE4.1 variant
-
-
-
2024-05-03
Richard Henderson
New
[PULL,04/10] util/bufferiszero: Remove useless prefetches
[PULL,01/10] util/bufferiszero: Remove SSE4.1 variant
-
-
-
2024-05-03
Richard Henderson
Accepted
[PULL,03/10] util/bufferiszero: Reorganize for early test for acceleration
[PULL,01/10] util/bufferiszero: Remove SSE4.1 variant
-
-
-
2024-05-03
Richard Henderson
Accepted
[PULL,02/10] util/bufferiszero: Remove AVX512 variant
[PULL,01/10] util/bufferiszero: Remove SSE4.1 variant
-
-
-
2024-05-03
Richard Henderson
Accepted
[PULL,01/10] util/bufferiszero: Remove SSE4.1 variant
[PULL,01/10] util/bufferiszero: Remove SSE4.1 variant
-
-
-
2024-05-03
Richard Henderson
Accepted
[PULL,00/10] bufferiszero improvements
-
-
-
2024-05-03
Richard Henderson
New
[v2,7/7] target/sparc: Split out do_ms16b
target/sparc: vis fixes
-
-
-
2024-05-02
Richard Henderson
Superseded
[v2,6/7] target/sparc: Fix FPMERGE
target/sparc: vis fixes
-
-
-
2024-05-02
Richard Henderson
Superseded
[v2,5/7] target/sparc: Fix FMULD8*X16
target/sparc: vis fixes
-
-
-
2024-05-02
Richard Henderson
Superseded
[v2,4/7] target/sparc: Fix FMUL8x16A{U,L}
target/sparc: vis fixes
-
-
-
2024-05-02
Richard Henderson
New
[v2,3/7] target/sparc: Fix FMUL8x16
target/sparc: vis fixes
-
-
-
2024-05-02
Richard Henderson
Superseded
[v2,2/7] target/sparc: Fix FEXPAND
target/sparc: vis fixes
-
-
-
2024-05-02
Richard Henderson
Superseded
[v2,1/7] linux-user/sparc: Add more hwcap bits for sparc64
target/sparc: vis fixes
-
-
-
2024-05-02
Richard Henderson
Superseded
[14/14] tests/tcg/s390x: Add per.S
target/s390x: Fix and improve PER
-
-
-
2024-05-02
Richard Henderson
New
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