From patchwork Wed Feb 9 13:48:07 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 94 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:39:55 -0000 Delivered-To: patches@linaro.org Received: by 10.147.124.5 with SMTP id b5cs144399yan; Wed, 9 Feb 2011 05:48:20 -0800 (PST) Received: by 10.204.121.138 with SMTP id h10mr19406612bkr.40.1297259296939; Wed, 09 Feb 2011 05:48:16 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk [81.2.115.146]) by mx.google.com with ESMTPS id b20si891846bkb.34.2011.02.09.05.48.15 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 09 Feb 2011 05:48:16 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.69) (envelope-from ) id 1PnAOy-0001JU-Og; Wed, 09 Feb 2011 13:48:12 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Christophe Lyon Subject: [PATCH 1/6] softfloat: Add float16 type and float16 NaN handling functions Date: Wed, 9 Feb 2011 13:48:07 +0000 Message-Id: <1297259292-5025-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1297259292-5025-1-git-send-email-peter.maydell@linaro.org> References: <1297259292-5025-1-git-send-email-peter.maydell@linaro.org> Add a float16 type to softfloat, rather than using bits16 directly. Also add the missing functions float16_is_quiet_nan(), float16_is_signaling_nan() and float16_maybe_silence_nan(), which are needed for the float16 conversion routines. Signed-off-by: Peter Maydell --- fpu/softfloat-specialize.h | 59 ++++++++++++++++++++++++++++++++++++++++++++ fpu/softfloat.c | 8 +++--- fpu/softfloat.h | 12 +++++++- 3 files changed, 73 insertions(+), 6 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index eb644b2..bc9a66c 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -57,6 +57,65 @@ typedef struct { } commonNaNT; /*---------------------------------------------------------------------------- +| The pattern for a default generated half-precision NaN. +*----------------------------------------------------------------------------*/ +#if defined(TARGET_ARM) +#define float16_default_nan 0x7E00 +#elif SNAN_BIT_IS_ONE +#define float16_default_nan 0x7DFF +#else +#define float16_default_nan 0xFE00 +#endif + +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point value `a' is a quiet +| NaN; otherwise returns 0. +*----------------------------------------------------------------------------*/ + +int float16_is_quiet_nan(float16 a) +{ +#if SNAN_BIT_IS_ONE + return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); +#else + return ((a & ~0x8000) >= 0x7c80); +#endif +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point value `a' is a signaling +| NaN; otherwise returns 0. +*----------------------------------------------------------------------------*/ + +int float16_is_signaling_nan(float16 a) +{ +#if SNAN_BIT_IS_ONE + return ((a & ~0x8000) >= 0x7c80); +#else + return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); +#endif +} + +/*---------------------------------------------------------------------------- +| Returns a quiet NaN if the half-precision floating point value `a' is a +| signaling NaN; otherwise returns `a'. +*----------------------------------------------------------------------------*/ +float16 float16_maybe_silence_nan(float16 a) +{ + if (float16_is_signaling_nan(a)) { +#if SNAN_BIT_IS_ONE +# if defined(TARGET_MIPS) || defined(TARGET_SH4) + return float16_default_nan; +# else +# error Rules for silencing a signaling NaN are target-specific +# endif +#else + a |= (1 << 9); +#endif + } + return a; +} + +/*---------------------------------------------------------------------------- | The pattern for a default generated single-precision NaN. *----------------------------------------------------------------------------*/ #if defined(TARGET_SPARC) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 17842f4..dc4492a 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2713,15 +2713,15 @@ float32 float64_to_float32( float64 a STATUS_PARAM ) | than the desired result exponent whenever `zSig' is a complete, normalized | significand. *----------------------------------------------------------------------------*/ -static bits16 packFloat16(flag zSign, int16 zExp, bits16 zSig) +static float16 packFloat16(flag zSign, int16 zExp, bits16 zSig) { return (((bits32)zSign) << 15) + (((bits32)zExp) << 10) + zSig; } /* Half precision floats come in two formats: standard IEEE and "ARM" format. The latter gains extra exponent range by omitting the NaN/Inf encodings. */ - -float32 float16_to_float32( bits16 a, flag ieee STATUS_PARAM ) + +float32 float16_to_float32(float16 a, flag ieee STATUS_PARAM) { flag aSign; int16 aExp; @@ -2753,7 +2753,7 @@ float32 float16_to_float32( bits16 a, flag ieee STATUS_PARAM ) return packFloat32( aSign, aExp + 0x70, aSig << 13); } -bits16 float32_to_float16( float32 a, flag ieee STATUS_PARAM) +float16 float32_to_float16(float32 a, flag ieee STATUS_PARAM) { flag aSign; int16 aExp; diff --git a/fpu/softfloat.h b/fpu/softfloat.h index 4a5345c..f773d67 100644 --- a/fpu/softfloat.h +++ b/fpu/softfloat.h @@ -118,6 +118,7 @@ enum { sane ABI should be able to see though these structs. However x86/gcc 3.x seems to struggle a bit, so leave them disabled by default. */ //#define USE_SOFTFLOAT_STRUCT_TYPES +typedef uint16_t float16; #ifdef USE_SOFTFLOAT_STRUCT_TYPES typedef struct { uint32_t v; @@ -253,8 +254,15 @@ float128 int64_to_float128( int64_t STATUS_PARAM ); /*---------------------------------------------------------------------------- | Software half-precision conversion routines. *----------------------------------------------------------------------------*/ -bits16 float32_to_float16( float32, flag STATUS_PARAM ); -float32 float16_to_float32( bits16, flag STATUS_PARAM ); +float16 float32_to_float16( float32, flag STATUS_PARAM ); +float32 float16_to_float32( float16, flag STATUS_PARAM ); + +/*---------------------------------------------------------------------------- +| Software half-precision operations. +*----------------------------------------------------------------------------*/ +int float16_is_quiet_nan( float16 ); +int float16_is_signaling_nan( float16 ); +float16 float16_maybe_silence_nan( float16 ); /*---------------------------------------------------------------------------- | Software IEC/IEEE single-precision conversion routines.