From patchwork Mon Feb 21 20:57:50 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 185 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:40:43 -0000 Delivered-To: patches@linaro.org Received: by 10.224.19.208 with SMTP id c16cs202820qab; Mon, 21 Feb 2011 12:57:58 -0800 (PST) Received: by 10.204.126.98 with SMTP id b34mr1651995bks.38.1298321876280; Mon, 21 Feb 2011 12:57:56 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk [81.2.115.146]) by mx.google.com with ESMTPS id l3si15887596bkb.24.2011.02.21.12.57.55 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 21 Feb 2011 12:57:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1PrcpN-0004Rj-O1; Mon, 21 Feb 2011 20:57:53 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 2/5] hw/arm_sysctl.c: Wire MCI register MMC card status bits to GPIO inputs Date: Mon, 21 Feb 2011 20:57:50 +0000 Message-Id: <1298321873-17064-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298321873-17064-1-git-send-email-peter.maydell@linaro.org> References: <1298321873-17064-1-git-send-email-peter.maydell@linaro.org> Implement some GPIO inputs which a board can connect up to set the MMC card status bits in the MCI register. Signed-off-by: Peter Maydell --- hw/arm_sysctl.c | 47 ++++++++++++++++++++++++++++++++++++++++++++++- hw/primecell.h | 4 ++++ 2 files changed, 50 insertions(+), 1 deletions(-) diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c index d8b062c..799b007 100644 --- a/hw/arm_sysctl.c +++ b/hw/arm_sysctl.c @@ -26,6 +26,7 @@ typedef struct { uint32_t nvflags; uint32_t resetlevel; uint32_t proc_id; + uint32_t sys_mci; } arm_sysctl_state; static const VMStateDescription vmstate_arm_sysctl = { @@ -44,6 +45,21 @@ static const VMStateDescription vmstate_arm_sysctl = { } }; +/* The PB926 actually uses a different format for + * its SYS_ID register. Fortunately the bits which are + * board type on later boards are distinct. + */ +#define BOARD_ID_PB926 0x100 +#define BOARD_ID_EB 0x140 +#define BOARD_ID_PBA8 0x178 +#define BOARD_ID_PBX 0x182 + +static int board_id(arm_sysctl_state *s) +{ + /* Extract the board ID field from the SYS_ID register value */ + return (s->sys_id >> 16) & 0xfff; +} + static void arm_sysctl_reset(DeviceState *d) { arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sysbus_from_qdev(d)); @@ -92,7 +108,7 @@ static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset) case 0x44: /* PCICTL */ return 1; case 0x48: /* MCI */ - return 0; + return s->sys_mci; case 0x4c: /* FLASH */ return 0; case 0x50: /* CLCD */ @@ -218,6 +234,34 @@ static CPUWriteMemoryFunc * const arm_sysctl_writefn[] = { arm_sysctl_write }; +static void arm_sysctl_gpio_set(void *opaque, int line, int level) +{ + arm_sysctl_state *s = (arm_sysctl_state *)opaque; + switch (line) { + case ARM_SYSCTL_GPIO_MMC_WPROT: + { + /* For PB926 and EB write-protect is bit 2 of SYS_MCI; + * for all later boards it is bit 1. + */ + int bit = 2; + if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) { + bit = 4; + } + s->sys_mci &= ~bit; + if (level) { + s->sys_mci |= bit; + } + break; + } + case ARM_SYSCTL_GPIO_MMC_CARDIN: + s->sys_mci &= ~1; + if (level) { + s->sys_mci |= 1; + } + break; + } +} + static int arm_sysctl_init1(SysBusDevice *dev) { arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev); @@ -227,6 +271,7 @@ static int arm_sysctl_init1(SysBusDevice *dev) arm_sysctl_writefn, s, DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); + qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2); /* ??? Save/restore. */ return 0; } diff --git a/hw/primecell.h b/hw/primecell.h index fb456ad..de7d6f2 100644 --- a/hw/primecell.h +++ b/hw/primecell.h @@ -11,4 +11,8 @@ void *pl080_init(uint32_t base, qemu_irq irq, int nchannels); /* arm_sysctl.c */ void arm_sysctl_init(uint32_t base, uint32_t sys_id, uint32_t proc_id); +/* arm_sysctl GPIO lines */ +#define ARM_SYSCTL_GPIO_MMC_WPROT 0 +#define ARM_SYSCTL_GPIO_MMC_CARDIN 1 + #endif