From patchwork Fri Mar 30 13:00:30 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7538 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 6F8EC23E42 for ; Fri, 30 Mar 2012 13:00:51 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 204C4A1807F for ; Fri, 30 Mar 2012 13:00:51 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so1328413iag.11 for ; Fri, 30 Mar 2012 06:00:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-forwarded-to:x-forwarded-for:delivered-to :received-spf:from:to:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=elYhw/kTxWyJgpWi2pH3DvPohLGEpVM+WNzvd1quizk=; b=Ft1ajy3jvFGCOPEt3F2VlnyeAQ5hylSbJysjjT9xlEn2pDabzYkOlswQ2xzQTQlq7j vKJKK9dCz+kGHO/55n0QyDKBmNJ+WJJj5MQMZcAhMCg7E44cTDTyvI5gGAcg5pLxUGQM blWAowDoEPLK7dbyo4Yj7Ke6Nc5gLYcNVzUL3woISeSMTXBYAZffih7Up82vSiiZKrIv DmvyMrFetdx39N5+CyOZRadqcUW8bZQHtT++G86NTvgh4Dw6eK6N9mDhwU3nUktLHXfp Q/QssmEbZxDa/nq5LtxzkImmSASos5MEgLgAJlXIOovVom2zKNXD97TrEtCDrrb4sZl7 SLOA== MIME-Version: 1.0 Received: by 10.50.45.234 with SMTP id q10mr1263271igm.54.1333112450884; Fri, 30 Mar 2012 06:00:50 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.5.205 with SMTP id 13csp21193ibw; Fri, 30 Mar 2012 06:00:49 -0700 (PDT) Received: by 10.68.223.42 with SMTP id qr10mr9326932pbc.127.1333112448055; Fri, 30 Mar 2012 06:00:48 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id t9si11887514pbv.25.2012.03.30.06.00.46 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 30 Mar 2012 06:00:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SDbRb-000113-7Y for patches@linaro.org; Fri, 30 Mar 2012 14:00:43 +0100 From: Peter Maydell To: patches@linaro.org Subject: [PATCH 02/14] target-arm: Move feature bit settings to CPU init fns Date: Fri, 30 Mar 2012 14:00:30 +0100 Message-Id: <1333112442-3871-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1333112442-3871-1-git-send-email-peter.maydell@linaro.org> References: <1333112442-3871-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQlU93psg/FIrefNXbreBR8XFXAFZ0YPzWqp2SK7+g+FBoMoUYDWKgnR/F1jvufranxHJgPM Move the setting of the feature bits from cpu_reset_model_id() to each CPU's instance init function. This requires us to move the features field in CPUARMState so that it is not cleared on reset. Signed-off-by: Peter Maydell --- target-arm/cpu.c | 155 +++++++++++++++++++++++++++++++++++++++++++++++++++ target-arm/cpu.h | 6 +- target-arm/helper.c | 96 ------------------------------- 3 files changed, 158 insertions(+), 99 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index a09e24e..0dad352 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -34,6 +34,11 @@ static void arm_cpu_reset(CPUState *s) cpu_state_reset(&cpu->env); } +static inline void set_feature(CPUARMState *env, int feature) +{ + env->features |= 1u << feature; +} + static void arm_cpu_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -44,162 +49,312 @@ static void arm_cpu_initfn(Object *obj) cpu->env.cpu_model_str = object_get_typename(obj); } +static void arm_cpu_postconfig_init(ARMCPU *cpu) +{ + /* This function is called as the last thing the init + * functions for the CPU model specific subclasses do, + * so it can do common actions based on feature bits, etc. + * When we have realize support it should probably become + * a realize function. + */ + CPUARMState *env = &cpu->env; + /* Some features automatically imply others: */ + if (arm_feature(env, ARM_FEATURE_V7)) { + set_feature(env, ARM_FEATURE_VAPA); + set_feature(env, ARM_FEATURE_THUMB2); + if (!arm_feature(env, ARM_FEATURE_M)) { + set_feature(env, ARM_FEATURE_V6K); + } else { + set_feature(env, ARM_FEATURE_V6); + } + } + if (arm_feature(env, ARM_FEATURE_V6K)) { + set_feature(env, ARM_FEATURE_V6); + set_feature(env, ARM_FEATURE_MVFR); + } + if (arm_feature(env, ARM_FEATURE_V6)) { + set_feature(env, ARM_FEATURE_V5); + if (!arm_feature(env, ARM_FEATURE_M)) { + set_feature(env, ARM_FEATURE_AUXCR); + } + } + if (arm_feature(env, ARM_FEATURE_V5)) { + set_feature(env, ARM_FEATURE_V4T); + } + if (arm_feature(env, ARM_FEATURE_M)) { + set_feature(env, ARM_FEATURE_THUMB_DIV); + } + if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { + set_feature(env, ARM_FEATURE_THUMB_DIV); + } + if (arm_feature(env, ARM_FEATURE_VFP4)) { + set_feature(env, ARM_FEATURE_VFP3); + } + if (arm_feature(env, ARM_FEATURE_VFP3)) { + set_feature(env, ARM_FEATURE_VFP); + } +} + /* CPU models */ static void arm926_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_VFP); cpu->midr = ARM_CPUID_ARM926; + arm_cpu_postconfig_init(cpu); } static void arm946_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_MPU); cpu->midr = ARM_CPUID_ARM946; + arm_cpu_postconfig_init(cpu); } static void arm1026_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_VFP); + set_feature(&cpu->env, ARM_FEATURE_AUXCR); cpu->midr = ARM_CPUID_ARM1026; + arm_cpu_postconfig_init(cpu); } static void arm1136_r2_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V6); + set_feature(&cpu->env, ARM_FEATURE_VFP); cpu->midr = ARM_CPUID_ARM1136_R2; + arm_cpu_postconfig_init(cpu); } static void arm1136_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V6K); + set_feature(&cpu->env, ARM_FEATURE_V6); + set_feature(&cpu->env, ARM_FEATURE_VFP); cpu->midr = ARM_CPUID_ARM1136; + arm_cpu_postconfig_init(cpu); } static void arm1176_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V6K); + set_feature(&cpu->env, ARM_FEATURE_VFP); + set_feature(&cpu->env, ARM_FEATURE_VAPA); cpu->midr = ARM_CPUID_ARM1176; + arm_cpu_postconfig_init(cpu); } static void arm11mpcore_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V6K); + set_feature(&cpu->env, ARM_FEATURE_VFP); + set_feature(&cpu->env, ARM_FEATURE_VAPA); cpu->midr = ARM_CPUID_ARM11MPCORE; + arm_cpu_postconfig_init(cpu); } static void cortex_m3_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); cpu->midr = ARM_CPUID_CORTEXM3; + arm_cpu_postconfig_init(cpu); } static void cortex_a8_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_VFP3); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); cpu->midr = ARM_CPUID_CORTEXA8; + arm_cpu_postconfig_init(cpu); } static void cortex_a9_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_VFP3); + set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + /* Note that A9 supports the MP extensions even for + * A9UP and single-core A9MP (which are both different + * and valid configurations; we don't model A9UP). + */ + set_feature(&cpu->env, ARM_FEATURE_V7MP); cpu->midr = ARM_CPUID_CORTEXA9; + arm_cpu_postconfig_init(cpu); } static void cortex_a15_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); + set_feature(&cpu->env, ARM_FEATURE_V7MP); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); cpu->midr = ARM_CPUID_CORTEXA15; + arm_cpu_postconfig_init(cpu); } static void ti925t_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V4T); + set_feature(&cpu->env, ARM_FEATURE_OMAPCP); cpu->midr = ARM_CPUID_TI925T; + arm_cpu_postconfig_init(cpu); } static void sa1100_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_STRONGARM); cpu->midr = ARM_CPUID_SA1100; + arm_cpu_postconfig_init(cpu); } static void sa1110_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_STRONGARM); cpu->midr = ARM_CPUID_SA1110; + arm_cpu_postconfig_init(cpu); } static void pxa250_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->midr = ARM_CPUID_PXA250; + arm_cpu_postconfig_init(cpu); } static void pxa255_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->midr = ARM_CPUID_PXA255; + arm_cpu_postconfig_init(cpu); } static void pxa260_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->midr = ARM_CPUID_PXA260; + arm_cpu_postconfig_init(cpu); } static void pxa261_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->midr = ARM_CPUID_PXA261; + arm_cpu_postconfig_init(cpu); } static void pxa262_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->midr = ARM_CPUID_PXA262; + arm_cpu_postconfig_init(cpu); } static void pxa270a0_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->midr = ARM_CPUID_PXA270_A0; + arm_cpu_postconfig_init(cpu); } static void pxa270a1_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->midr = ARM_CPUID_PXA270_A1; + arm_cpu_postconfig_init(cpu); } static void pxa270b0_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->midr = ARM_CPUID_PXA270_B0; + arm_cpu_postconfig_init(cpu); } static void pxa270b1_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->midr = ARM_CPUID_PXA270_B1; + arm_cpu_postconfig_init(cpu); } static void pxa270c0_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->midr = ARM_CPUID_PXA270_C0; + arm_cpu_postconfig_init(cpu); } static void pxa270c5_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); + set_feature(&cpu->env, ARM_FEATURE_V7MP); cpu->midr = ARM_CPUID_PXA270_C5; + arm_cpu_postconfig_init(cpu); } static void arm_any_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); cpu->midr = ARM_CPUID_ANY; + arm_cpu_postconfig_init(cpu); } typedef struct ARMCPUInfo { diff --git a/target-arm/cpu.h b/target-arm/cpu.h index e176c5f..85246dd 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -170,9 +170,6 @@ typedef struct CPUARMState { uint32_t teecr; uint32_t teehbr; - /* Internal CPU feature flags. */ - uint32_t features; - /* VFP coprocessor state. */ struct { float64 regs[32]; @@ -225,6 +222,9 @@ typedef struct CPUARMState { /* These fields after the common ones so they are preserved on reset. */ + /* Internal CPU feature flags. */ + uint32_t features; + /* Coprocessor IO used by peripherals */ struct { ARMReadCPFunc *cp_read; diff --git a/target-arm/helper.c b/target-arm/helper.c index 4748f80..af752e4 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -47,46 +47,30 @@ static uint32_t arm1176_cp15_c0_c1[8] = static uint32_t arm1176_cp15_c0_c2[8] = { 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 }; -static inline void set_feature(CPUARMState *env, int feature) -{ - env->features |= 1u << feature; -} - static void cpu_reset_model_id(CPUARMState *env, uint32_t id) { switch (id) { case ARM_CPUID_ARM926: - set_feature(env, ARM_FEATURE_V5); - set_feature(env, ARM_FEATURE_VFP); env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090; env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00090078; break; case ARM_CPUID_ARM946: - set_feature(env, ARM_FEATURE_V5); - set_feature(env, ARM_FEATURE_MPU); env->cp15.c0_cachetype = 0x0f004006; env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_ARM1026: - set_feature(env, ARM_FEATURE_V5); - set_feature(env, ARM_FEATURE_VFP); - set_feature(env, ARM_FEATURE_AUXCR); env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0; env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00090078; break; case ARM_CPUID_ARM1136: /* This is the 1136 r1, which is a v6K core */ - set_feature(env, ARM_FEATURE_V6K); - /* Fall through */ case ARM_CPUID_ARM1136_R2: /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an * older core than plain "arm1136". In particular this does not * have the v6K features. */ - set_feature(env, ARM_FEATURE_V6); - set_feature(env, ARM_FEATURE_VFP); /* These ID register values are correct for 1136 but may be wrong * for 1136_r2 (in particular r0p2 does not actually implement most * of the ID registers). @@ -100,9 +84,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM1176: - set_feature(env, ARM_FEATURE_V6K); - set_feature(env, ARM_FEATURE_VFP); - set_feature(env, ARM_FEATURE_VAPA); env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; @@ -112,9 +93,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM11MPCORE: - set_feature(env, ARM_FEATURE_V6K); - set_feature(env, ARM_FEATURE_VFP); - set_feature(env, ARM_FEATURE_VAPA); env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; @@ -123,10 +101,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_cachetype = 0x1dd20d2; break; case ARM_CPUID_CORTEXA8: - set_feature(env, ARM_FEATURE_V7); - set_feature(env, ARM_FEATURE_VFP3); - set_feature(env, ARM_FEATURE_NEON); - set_feature(env, ARM_FEATURE_THUMB2EE); env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100; @@ -140,16 +114,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXA9: - set_feature(env, ARM_FEATURE_V7); - set_feature(env, ARM_FEATURE_VFP3); - set_feature(env, ARM_FEATURE_VFP_FP16); - set_feature(env, ARM_FEATURE_NEON); - set_feature(env, ARM_FEATURE_THUMB2EE); - /* Note that A9 supports the MP extensions even for - * A9UP and single-core A9MP (which are both different - * and valid configurations; we don't model A9UP). - */ - set_feature(env, ARM_FEATURE_V7MP); env->vfp.xregs[ARM_VFP_FPSID] = 0x41033090; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222; env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111; @@ -162,14 +126,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXA15: - set_feature(env, ARM_FEATURE_V7); - set_feature(env, ARM_FEATURE_VFP4); - set_feature(env, ARM_FEATURE_VFP_FP16); - set_feature(env, ARM_FEATURE_NEON); - set_feature(env, ARM_FEATURE_THUMB2EE); - set_feature(env, ARM_FEATURE_ARM_DIV); - set_feature(env, ARM_FEATURE_V7MP); - set_feature(env, ARM_FEATURE_GENERIC_TIMER); env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0; env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222; env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111; @@ -183,22 +139,11 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXM3: - set_feature(env, ARM_FEATURE_V7); - set_feature(env, ARM_FEATURE_M); break; case ARM_CPUID_ANY: /* For userspace emulation. */ - set_feature(env, ARM_FEATURE_V7); - set_feature(env, ARM_FEATURE_VFP4); - set_feature(env, ARM_FEATURE_VFP_FP16); - set_feature(env, ARM_FEATURE_NEON); - set_feature(env, ARM_FEATURE_THUMB2EE); - set_feature(env, ARM_FEATURE_ARM_DIV); - set_feature(env, ARM_FEATURE_V7MP); break; case ARM_CPUID_TI915T: case ARM_CPUID_TI925T: - set_feature(env, ARM_FEATURE_V4T); - set_feature(env, ARM_FEATURE_OMAPCP); env->cp15.c0_cachetype = 0x5109149; env->cp15.c1_sys = 0x00000070; env->cp15.c15_i_max = 0x000; @@ -209,8 +154,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_PXA260: case ARM_CPUID_PXA261: case ARM_CPUID_PXA262: - set_feature(env, ARM_FEATURE_V5); - set_feature(env, ARM_FEATURE_XSCALE); /* JTAG_ID is ((id << 28) | 0x09265013) */ env->cp15.c0_cachetype = 0xd172172; env->cp15.c1_sys = 0x00000078; @@ -221,17 +164,13 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_PXA270_B1: case ARM_CPUID_PXA270_C0: case ARM_CPUID_PXA270_C5: - set_feature(env, ARM_FEATURE_V5); - set_feature(env, ARM_FEATURE_XSCALE); /* JTAG_ID is ((id << 28) | 0x09265013) */ - set_feature(env, ARM_FEATURE_IWMMXT); env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; env->cp15.c0_cachetype = 0xd172172; env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_SA1100: case ARM_CPUID_SA1110: - set_feature(env, ARM_FEATURE_STRONGARM); env->cp15.c1_sys = 0x00000070; break; default: @@ -239,41 +178,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; } - /* Some features automatically imply others: */ - if (arm_feature(env, ARM_FEATURE_V7)) { - set_feature(env, ARM_FEATURE_VAPA); - set_feature(env, ARM_FEATURE_THUMB2); - if (!arm_feature(env, ARM_FEATURE_M)) { - set_feature(env, ARM_FEATURE_V6K); - } else { - set_feature(env, ARM_FEATURE_V6); - } - } - if (arm_feature(env, ARM_FEATURE_V6K)) { - set_feature(env, ARM_FEATURE_V6); - set_feature(env, ARM_FEATURE_MVFR); - } - if (arm_feature(env, ARM_FEATURE_V6)) { - set_feature(env, ARM_FEATURE_V5); - if (!arm_feature(env, ARM_FEATURE_M)) { - set_feature(env, ARM_FEATURE_AUXCR); - } - } - if (arm_feature(env, ARM_FEATURE_V5)) { - set_feature(env, ARM_FEATURE_V4T); - } - if (arm_feature(env, ARM_FEATURE_M)) { - set_feature(env, ARM_FEATURE_THUMB_DIV); - } - if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { - set_feature(env, ARM_FEATURE_THUMB_DIV); - } - if (arm_feature(env, ARM_FEATURE_VFP4)) { - set_feature(env, ARM_FEATURE_VFP3); - } - if (arm_feature(env, ARM_FEATURE_VFP3)) { - set_feature(env, ARM_FEATURE_VFP); - } } /* TODO Move contents into arm_cpu_reset() in cpu.c,