From patchwork Sun Apr 15 13:46:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7862 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 92BD923E47 for ; Sun, 15 Apr 2012 13:47:01 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 577EDA181A5 for ; Sun, 15 Apr 2012 13:47:01 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so8543068iag.11 for ; Sun, 15 Apr 2012 06:47:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=IW17ifdu96mQdoeXSvothCOhrfA8cy/RnBcGRl0RCfc=; b=Ay0WY2ZzrsP6IHvG54J45dhm293Sfjh242a+7Em2t7fOAQn2lhEpbfdzjfHXZy6ULB uUDmA/NcPzEarrMu6ba6xEe6P4GygwM3IqXfdzzzrLGAkjdpKS8P0wioIEjXUofe9Da+ JPU1E3N57Hq9SePBVlBhWVIMNEG8Ak5CAI8Wt9NAGar78l+o0okhf1Ct4MGaCfW653Ss TWc9WU+gu7EwaMW0I8UNU4fuNodAmRjlvaWjTEsN/fMNVp56/XMj4dZ+23CAfi0bt5Sr +DR3qrk4zf5Y43+jI6T8D35AUirFppE11muhdWqGnVtIbbiRJvX2dDqGLoXlKsNEU8ss HyeQ== Received: by 10.50.188.199 with SMTP id gc7mr3148390igc.40.1334497621136; Sun, 15 Apr 2012 06:47:01 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp22275ibj; Sun, 15 Apr 2012 06:47:00 -0700 (PDT) Received: by 10.180.92.130 with SMTP id cm2mr10874641wib.4.1334497619894; Sun, 15 Apr 2012 06:46:59 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id s6si4822914wiz.17.2012.04.15.06.46.59 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 15 Apr 2012 06:46:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJPmc-0000Et-Md; Sun, 15 Apr 2012 14:46:26 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [PATCH 12/32] target-arm: Convert generic timer cp15 regs Date: Sun, 15 Apr 2012 14:46:05 +0100 Message-Id: <1334497585-867-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> References: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQkP9OQHYIKMvEpd5qYVFH543ZWS5n+DMZyAl+SOj/HnKYDpBJEmu/EjFN6pU13QCvVfr9/o Convert the (dummy) generic timer cp15 implementation. Signed-off-by: Peter Maydell --- target-arm/helper.c | 23 +++++++++++------------ 1 files changed, 11 insertions(+), 12 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index c61e0de..620e652 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -323,6 +323,14 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo generic_timer_cp_reginfo[] = { + /* Dummy implementation: RAZ/WI the whole crn=14 space */ + { .name = "GENERIC_TIMER", .cp = 15, .crn = 14, + .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -359,6 +367,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { define_arm_cp_regs(env, t2ee_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { + define_arm_cp_regs(env, generic_timer_cp_reginfo); + } } CPUARMState *cpu_arm_init(const char *cpu_model) @@ -1708,12 +1719,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) goto bad_reg; } break; - case 14: /* Generic timer */ - if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { - /* Dummy implementation: RAZ/WI for all */ - break; - } - goto bad_reg; case 15: /* Implementation specific. */ if (arm_feature(env, ARM_FEATURE_XSCALE)) { if (op2 == 0 && crm == 1) { @@ -2053,12 +2058,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) default: goto bad_reg; } - case 14: /* Generic timer */ - if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { - /* Dummy implementation: RAZ/WI for all */ - return 0; - } - goto bad_reg; case 15: /* Implementation specific. */ if (arm_feature(env, ARM_FEATURE_XSCALE)) { if (op2 == 0 && crm == 1)