From patchwork Sun Apr 15 13:46:12 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7840 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 22FD823E47 for ; Sun, 15 Apr 2012 13:46:38 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id DCC1AA181A5 for ; Sun, 15 Apr 2012 13:46:37 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so8543068iag.11 for ; Sun, 15 Apr 2012 06:46:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=bIBvBNrHXKMBfh898GzXElQi+VHtMhIPdPWmg/Qb58g=; b=kWd74QRc5npIBwq5uND6F2Q3cg5V6uRLEbSYpBj7uNM+1pX9YUREtkRUSeiX3UHjQ2 0Csl2ymut0Ftlt5gLhl6RRRblAuF+WVtR52M1ylGUP6QoATvKUiwMYM3dwoKYZMAvDRN QnVQn7WWSVZZFHQjs6UvmaPwdvhMSXjIQ6qN9zXqye+iqSn/33+d9TJpLMOiSu6uN/UA Ji2ATk7CuprHcLInkkWnXkI/bFjj9921XJJC7jgaleOme8LY2ZvEdzPAcyyAIVA3KJN1 AUXw43OB4+S7UBxRuil8RRZ8bpMYJKW7GXbFO0zOGcWJcchA07uG/A81QdQynAlIumMw e5JQ== Received: by 10.42.152.134 with SMTP id i6mr4886825icw.27.1334497597685; Sun, 15 Apr 2012 06:46:37 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp22211ibj; Sun, 15 Apr 2012 06:46:36 -0700 (PDT) Received: by 10.216.208.21 with SMTP id p21mr4819937weo.12.1334497595786; Sun, 15 Apr 2012 06:46:35 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id i6si4821117wia.22.2012.04.15.06.46.33 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 15 Apr 2012 06:46:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJPmd-0000F7-6Y; Sun, 15 Apr 2012 14:46:27 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [PATCH 19/32] target-arm: Convert cp15 MMU TLB control Date: Sun, 15 Apr 2012 14:46:12 +0100 Message-Id: <1334497585-867-20-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> References: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQlv2+rTE8r5LeYtGFgugj+aj9KVQ6UrI2M/sx+Kv1IsiOCE75ArrMS7V/Y+JzuWYEHNh4Q+ Convert cp15 MMU TLB control (crn=8) to new scheme. Signed-off-by: Peter Maydell --- target-arm/helper.c | 63 ++++++++++++++++++++++++++++++++++---------------- 1 files changed, 43 insertions(+), 20 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 6a7ac5b..32fa49a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -93,6 +93,38 @@ static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, return 0; } +static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate all (TLBIALL) */ + tlb_flush(env, 1); + return 0; +} + +static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ + tlb_flush_page(env, value & TARGET_PAGE_MASK); + return 0; +} + +static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate by ASID (TLBIASID) */ + tlb_flush(env, value == 0); + return 0; +} + +static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ + tlb_flush_page(env, value & TARGET_PAGE_MASK); + return 0; +} + static const ARMCPRegInfo cp_reginfo[] = { /* DBGDIDR: just RAZ. In particular this means the "debug architecture * version" bits will read as a reserved value, which should cause @@ -116,6 +148,17 @@ static const ARMCPRegInfo cp_reginfo[] = { */ { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, + /* MMU TLB control. Note that the wildcarding means we cover not just + * the unified TLB ops but also the dside/iside/inner-shareable variants. + */ + { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, + .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, }, + { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, + .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, }, + { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, + .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, }, + { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, + .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, }, REGINFO_SENTINEL }; @@ -1823,24 +1866,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) } } break; - case 8: /* MMU TLB control. */ - switch (op2) { - case 0: /* Invalidate all (TLBIALL) */ - tlb_flush(env, 1); - break; - case 1: /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ - tlb_flush_page(env, val & TARGET_PAGE_MASK); - break; - case 2: /* Invalidate by ASID (TLBIASID) */ - tlb_flush(env, val == 0); - break; - case 3: /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ - tlb_flush_page(env, val & TARGET_PAGE_MASK); - break; - default: - goto bad_reg; - } - break; case 9: if (arm_feature(env, ARM_FEATURE_OMAPCP)) break; @@ -2053,8 +2078,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) /* FIXME: Should only clear Z flag if destination is r15. */ env->ZF = 0; return 0; - case 8: /* MMU TLB control. */ - goto bad_reg; case 9: switch (crm) { case 0: /* Cache lockdown */