From patchwork Wed May 2 17:12:04 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8364 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id A4E4C23E37 for ; Wed, 2 May 2012 17:12:29 +0000 (UTC) Received: from mail-yx0-f180.google.com (mail-yx0-f180.google.com [209.85.213.180]) by fiordland.canonical.com (Postfix) with ESMTP id 75D83A1841B for ; Wed, 2 May 2012 17:12:29 +0000 (UTC) Received: by mail-yx0-f180.google.com with SMTP id l4so1117349yen.11 for ; Wed, 02 May 2012 10:12:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=n7BbSucEY71o5BqPjwrbIOcoRnZmQjsOttfuWZgObbM=; b=lvh3C/WdDu797nz/cUIomqYdt7kowInqRoCy2BQUXGEk9QHnvdpcd93A6x/KfiNdnc wOrdhMvmen/Y7/9prGZBkmH6AGqLg3H/U3uwsX0yuVPxTV1+l2de0w9ILc3t/q5iEoBU ZOk6sc25nOvQOybz7xaQa9q2Sy3r1CvvDWmew/nGIt9dJYrigLXocGqkU1uNXrqV8GCm /NQIxIdrGABoM2xgzMBknb1aFfV2BQV6023C5r+jTH8YMcCd9xc7E6Vkqb3KXYKXj6vr GMD4WYEwegk4kJINgEdktqlOWT07OWvzuc/aRt+XVi6bLfoF8x7Sh/r0MF3V2vMVwhSN NyWw== Received: by 10.50.47.131 with SMTP id d3mr5965074ign.33.1335978749132; Wed, 02 May 2012 10:12:29 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.137.198 with SMTP id x6csp267517ibt; Wed, 2 May 2012 10:12:27 -0700 (PDT) Received: by 10.180.85.70 with SMTP id f6mr16182316wiz.5.1335978746978; Wed, 02 May 2012 10:12:26 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id n16si2772790wee.27.2012.05.02.10.12.26 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 02 May 2012 10:12:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SPd65-0008Te-3D; Wed, 02 May 2012 18:12:13 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [PATCH 1/9] hw/arm_gic: Remove NVIC ifdefs from gic_state struct Date: Wed, 2 May 2012 18:12:04 +0100 Message-Id: <1335978732-32559-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org> References: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQmZzw66osul/Mx5Ke5h4LMFSw5pWVlDrr14vP8TBhO1swKfBp+UI3VVpz2qLQvDpNFKU7Kp Remove some NVIC ifdefs from the gic_state struct and its state save/load functions. This means there are some fields in it which are present for the NVIC but not used, but means it always has the same layout and can be pulled out into a common subclass. Note that the addition of irq_target[] to the save/load struct for the NVIC requires a vmstate version bump. Signed-off-by: Peter Maydell Reviewed-by: Andreas Färber --- hw/arm_gic.c | 15 +++------------ 1 files changed, 3 insertions(+), 12 deletions(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index 72298b4..17b2eba 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -108,9 +108,7 @@ typedef struct gic_state int cpu_enabled[NCPU]; gic_irq_state irq_state[GIC_MAXIRQ]; -#ifndef NVIC int irq_target[GIC_MAXIRQ]; -#endif int priority1[GIC_INTERNAL][NCPU]; int priority2[GIC_MAXIRQ - GIC_INTERNAL]; int last_active[GIC_MAXIRQ][NCPU]; @@ -120,18 +118,14 @@ typedef struct gic_state int running_priority[NCPU]; int current_pending[NCPU]; -#if NCPU > 1 uint32_t num_cpu; -#endif MemoryRegion iomem; /* Distributor */ -#ifndef NVIC /* This is just so we can have an opaque pointer which identifies * both this GIC and which CPU interface we should be accessing. */ struct gic_state *backref[NCPU]; MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */ -#endif uint32_t num_irq; } gic_state; @@ -800,9 +794,7 @@ static void gic_save(QEMUFile *f, void *opaque) qemu_put_be32(f, s->priority2[i]); } for (i = 0; i < s->num_irq; i++) { -#ifndef NVIC qemu_put_be32(f, s->irq_target[i]); -#endif qemu_put_byte(f, s->irq_state[i].enabled); qemu_put_byte(f, s->irq_state[i].pending); qemu_put_byte(f, s->irq_state[i].active); @@ -818,8 +810,9 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id) int i; int j; - if (version_id != 2) + if (version_id != 3) { return -EINVAL; + } s->enabled = qemu_get_be32(f); for (i = 0; i < NUM_CPU(s); i++) { @@ -837,9 +830,7 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id) s->priority2[i] = qemu_get_be32(f); } for (i = 0; i < s->num_irq; i++) { -#ifndef NVIC s->irq_target[i] = qemu_get_be32(f); -#endif s->irq_state[i].enabled = qemu_get_byte(f); s->irq_state[i].pending = qemu_get_byte(f); s->irq_state[i].active = qemu_get_byte(f); @@ -914,7 +905,7 @@ static void gic_init(gic_state *s, int num_irq) } #endif - register_savevm(NULL, "arm_gic", -1, 2, gic_save, gic_load, s); + register_savevm(NULL, "arm_gic", -1, 3, gic_save, gic_load, s); } #ifndef NVIC