From patchwork Wed May 2 17:12:06 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8362 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 0F7B923E37 for ; Wed, 2 May 2012 17:12:26 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id CDB33A1841B for ; Wed, 2 May 2012 17:12:25 +0000 (UTC) Received: by mail-yw0-f52.google.com with SMTP id p61so1132622yhp.11 for ; Wed, 02 May 2012 10:12:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=Lnv94xAwDnBAbluSYx9qFsRVDD6uTskmSR+fmBqDqIc=; b=dATB9rtlzC5ldGXytcZV4Bcwc7uer0C3+vpNKlDSQh/1s8DOkQ5DgS8PvtIn1u5hFR h/dd/T/LIUGszk0xWR0jmUE3rT8VSB0HeRTRsteAxvMjTrhJceIwovBJEzK3t4Kpm6q8 /tae2rIOkoSIJe/SDbOraAyPLri2utkQNWKmdL23teYi1X5bOG7svDdIX1VvXzv8+X5J /GLvN9nnUJ/oFNzbB7IJ0slkgQJkK3JYg4pSrWW4oBE8SIilh6Mc4hwGBXv9pjSxIbyg zWzfFGWZyboyZFDQ6qZvUDHG7cGbbD/SJSAf9q2w0yBxCPtopxB5XPoPvADhPnMSvJRA FQdA== Received: by 10.42.142.71 with SMTP id r7mr7126566icu.7.1335978745455; Wed, 02 May 2012 10:12:25 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.137.198 with SMTP id x6csp267502ibt; Wed, 2 May 2012 10:12:19 -0700 (PDT) Received: by 10.68.194.227 with SMTP id hz3mr42544570pbc.23.1335978738533; Wed, 02 May 2012 10:12:18 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id kl4si686014pbc.201.2012.05.02.10.12.17 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 02 May 2012 10:12:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SPd65-0008Ti-7y; Wed, 02 May 2012 18:12:13 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [PATCH 3/9] hw/arm_gic: Move NVIC specific reset to armv7m_nvic_reset Date: Wed, 2 May 2012 18:12:06 +0100 Message-Id: <1335978732-32559-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org> References: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQlRvyFSIm7EOPgHdCnCry5KhCD3uENvW9/kXkghefBfVEPuExB98lloCfWt2zlVbFqTBdpY Move the NVIC specific bits of reset to the NVIC's own reset function, rather than using ifdefs in the common arm_gic reset. Signed-off-by: Peter Maydell --- hw/arm_gic.c | 10 ---------- hw/armv7m_nvic.c | 7 +++++++ 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index 2d8ceb8..3293ae4 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -743,23 +743,13 @@ static void gic_reset(DeviceState *dev) s->current_pending[i] = 1023; s->running_irq[i] = 1023; s->running_priority[i] = 0x100; -#ifdef NVIC - /* The NVIC doesn't have per-cpu interfaces, so enable by default. */ - s->cpu_enabled[i] = 1; -#else s->cpu_enabled[i] = 0; -#endif } for (i = 0; i < 16; i++) { GIC_SET_ENABLED(i, ALL_CPU_MASK); GIC_SET_TRIGGER(i); } -#ifdef NVIC - /* The NVIC is always enabled. */ - s->enabled = 1; -#else s->enabled = 0; -#endif } static void gic_save(QEMUFile *f, void *opaque) diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c index 99a87a2..653c011 100644 --- a/hw/armv7m_nvic.c +++ b/hw/armv7m_nvic.c @@ -382,6 +382,13 @@ static void armv7m_nvic_reset(DeviceState *dev) { nvic_state *s = FROM_SYSBUSGIC(nvic_state, sysbus_from_qdev(dev)); gic_reset(&s->gic.busdev.qdev); + /* Common GIC reset resets to disabled; the NVIC doesn't have + * per-CPU interfaces so mark our non-existent CPU interface + * as enabled by default. + */ + s->gic.cpu_enabled[0] = 1; + /* The NVIC as a whole is always enabled. */ + s->gic.enabled = 1; systick_reset(s); }