From patchwork Mon May 14 19:03:09 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8605 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 0EA1623E61 for ; Mon, 14 May 2012 19:03:41 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id BD486A18821 for ; Mon, 14 May 2012 19:03:40 +0000 (UTC) Received: by yhpp61 with SMTP id p61so5801914yhp.11 for ; Mon, 14 May 2012 12:03:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=1Hg5VNKbkn3k37I85twRnHdMZKzoYGkq533ertIxRyY=; b=VWxAZjxzWnhiznJGdfb7KEpQi/YBsZPGGdiAmPdYS8wxmlcXWRWF6IkHkxWPVyov8l zMKMR7qs5uCiWq3zCkXj+tOlQRruSxYbsIYzRPGvM4BW4pLCDBNkRq7N1IYYl+XME7ex k84kaM8myaA8E6fbB2G7R20441HU6TvEs/ltkOA137Xq8QnnZFBj0lSxcmlhMtXSMGOu 2P3drrSl4hV3lXnpCQirQN7aHLBoQ3a6GKiOfNcMvEZytc7AtHFV2nmJacYc2ZAS7iri 7LdY8qfSmL8pOx9NtepecVk36kgtQbVNu6Q9CmEf+Hx4Ll7kHQunpy5YnVeZoOt+G5Eu rPiA== Received: by 10.42.119.129 with SMTP id b1mr4276320icr.48.1337022220152; Mon, 14 May 2012 12:03:40 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.35.72 with SMTP id o8csp365931ibd; Mon, 14 May 2012 12:03:38 -0700 (PDT) Received: by 10.180.92.130 with SMTP id cm2mr881717wib.4.1337022216285; Mon, 14 May 2012 12:03:36 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id he5si20511974wib.44.2012.05.14.12.03.35 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 14 May 2012 12:03:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SU0YP-0005n8-26; Mon, 14 May 2012 20:03:33 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rusty Russell Subject: [PATCH qom-next v2 10/33] target-arm: Convert WFI/barriers special cases to cp_reginfo Date: Mon, 14 May 2012 20:03:09 +0100 Message-Id: <1337022212-22219-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> References: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQmoZUQvVbXy/mfK/xFqqUpNVRh1zZIpfhox7L7DHLQRGs+7jfaIXcJueHhcLy+nnv9geHTT Convert the various WFI and barrier instruction special cases to use cp_reginfo infrastructure. Signed-off-by: Peter Maydell --- target-arm/helper.c | 42 +++++++++++++++++++++++++++++++++++++++ target-arm/translate.c | 51 ------------------------------------------------ 2 files changed, 42 insertions(+), 51 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 99b4e6e..58bc291 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -71,6 +71,38 @@ static const ARMCPRegInfo cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo not_v6_cp_reginfo[] = { + /* Not all pre-v6 cores implemented this WFI, so this is slightly + * over-broad. + */ + { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, + .access = PL1_W, .type = ARM_CP_WFI }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo not_v7_cp_reginfo[] = { + /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which + * is UNPREDICTABLE; we choose to NOP as most implementations do). + */ + { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, + .access = PL1_W, .type = ARM_CP_WFI }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo v6_cp_reginfo[] = { + /* prefetch by MVA in v6, NOP in v7 */ + { .name = "MVA_prefetch", + .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, + .access = PL1_W, .type = ARM_CP_NOP }, + { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, + .access = PL0_W, .type = ARM_CP_NOP }, + { .name = "ISB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, + .access = PL0_W, .type = ARM_CP_NOP }, + { .name = "ISB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, + .access = PL0_W, .type = ARM_CP_NOP }, + REGINFO_SENTINEL +}; + static const ARMCPRegInfo v7_cp_reginfo[] = { /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped * debug components @@ -79,6 +111,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, { .name = "DBGDRAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ + { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, + .access = PL1_W, .type = ARM_CP_NOP }, REGINFO_SENTINEL }; @@ -134,8 +169,15 @@ void register_cp_regs_for_features(ARMCPU *cpu) } define_arm_cp_regs(cpu, cp_reginfo); + if (arm_feature(env, ARM_FEATURE_V6)) { + define_arm_cp_regs(cpu, v6_cp_reginfo); + } else { + define_arm_cp_regs(cpu, not_v6_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_V7)) { define_arm_cp_regs(cpu, v7_cp_reginfo); + } else { + define_arm_cp_regs(cpu, not_v7_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { define_arm_cp_regs(cpu, t2ee_cp_reginfo); diff --git a/target-arm/translate.c b/target-arm/translate.c index ba1bb94..a4429ea 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2541,57 +2541,6 @@ static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn) /* cdp */ return 1; } - /* We special case a number of cp15 instructions which were used - * for things which are real instructions in ARMv7. This allows - * them to work in linux-user mode which doesn't provide functional - * get_cp15/set_cp15 helpers, and is more efficient anyway. - */ - switch ((insn & 0x0fff0fff)) { - case 0x0e070f90: - /* 0,c7,c0,4: Standard v6 WFI (also used in some pre-v6 cores). - * In v7, this must NOP. - */ - if (IS_USER(s)) { - return 1; - } - if (!arm_feature(env, ARM_FEATURE_V7)) { - /* Wait for interrupt. */ - gen_set_pc_im(s->pc); - s->is_jmp = DISAS_WFI; - } - return 0; - case 0x0e070f58: - /* 0,c7,c8,2: Not all pre-v6 cores implemented this WFI, - * so this is slightly over-broad. - */ - if (!IS_USER(s) && !arm_feature(env, ARM_FEATURE_V6)) { - /* Wait for interrupt. */ - gen_set_pc_im(s->pc); - s->is_jmp = DISAS_WFI; - return 0; - } - /* Otherwise continue to handle via helper function. - * In particular, on v7 and some v6 cores this is one of - * the VA-PA registers. - */ - break; - case 0x0e070f3d: - /* 0,c7,c13,1: prefetch-by-MVA in v6, NOP in v7 */ - if (arm_feature(env, ARM_FEATURE_V6)) { - return IS_USER(s) ? 1 : 0; - } - break; - case 0x0e070f95: /* 0,c7,c5,4 : ISB */ - case 0x0e070f9a: /* 0,c7,c10,4: DSB */ - case 0x0e070fba: /* 0,c7,c10,5: DMB */ - /* Barriers in both v6 and v7 */ - if (arm_feature(env, ARM_FEATURE_V6)) { - return 0; - } - break; - default: - break; - } if (IS_USER(s) && !cp15_user_ok(env, insn)) { return 1;