From patchwork Mon May 14 19:03:10 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8635 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id BC35223EAB for ; Mon, 14 May 2012 19:27:15 +0000 (UTC) Received: from mail-yx0-f180.google.com (mail-yx0-f180.google.com [209.85.213.180]) by fiordland.canonical.com (Postfix) with ESMTP id 8B113A1880F for ; Mon, 14 May 2012 19:27:15 +0000 (UTC) Received: by mail-yx0-f180.google.com with SMTP id q6so5822442yen.11 for ; Mon, 14 May 2012 12:27:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=8qLUJeGJ2cprz1R+eRmsB0pR88zwTSAaxzC+yttxgTI=; b=amDkW/TB3XeF1yHaMMO4hq1FS7vBcHEin2kTgjgblME4egtoajd7ZvsNahn21lI5Zm 6OajMvcnn1QRgyxJw/wuAViWAniYQJXdtDjAPRg6O/ODAGx3W4YB70tlh4kRdMOhuQxq wbbpInc8KcnxVW5g0PmjQj4bHRSGsISLRb7AMN56Qi92NpOqa7Nc3ryF1Ol1l7j+vknb KSMRas3gUerHPri+4/DVkZoip5lOxXArkoFFrq+HyXgq77JDPgpYjrIiSE6NuZovcXKQ Z+n3nKCnLUvZBgcuBfChvUN9XrQVNP7zjyUepMM68Z9HFsUOx3CJTpzOQInWMm0bkj1f +UxA== Received: by 10.50.195.234 with SMTP id ih10mr277494igc.0.1337023635101; Mon, 14 May 2012 12:27:15 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.35.72 with SMTP id o8csp367283ibd; Mon, 14 May 2012 12:27:13 -0700 (PDT) Received: by 10.180.78.9 with SMTP id x9mr6970925wiw.18.1337023633067; Mon, 14 May 2012 12:27:13 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id n52si14144810wed.91.2012.05.14.12.27.12 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 14 May 2012 12:27:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SU0YP-0005nA-4H; Mon, 14 May 2012 20:03:33 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rusty Russell Subject: [PATCH qom-next v2 11/33] target-arm: Convert TLS registers Date: Mon, 14 May 2012 20:03:10 +0100 Message-Id: <1337022212-22219-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> References: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQmQB3YcjmD7hvVk1dLK7qS6yZoS9Jj4/TrdQFBi41ocMxGZFRwhSNT3oyQ2NJcuYXCy41ek Convert TLS registers to the new cp15 framework Signed-off-by: Peter Maydell --- target-arm/helper.c | 19 +++++++++++++++ target-arm/translate.c | 58 ------------------------------------------------ 2 files changed, 19 insertions(+), 58 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 58bc291..60bf03c 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -159,6 +159,22 @@ static const ARMCPRegInfo t2ee_cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo v6k_cp_reginfo[] = { + { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, + .access = PL0_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c13_tls1), + .resetvalue = 0 }, + { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, + .access = PL0_R|PL1_W, + .fieldoffset = offsetof(CPUARMState, cp15.c13_tls2), + .resetvalue = 0 }, + { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c13_tls3), + .resetvalue = 0 }, + REGINFO_SENTINEL +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -174,6 +190,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) } else { define_arm_cp_regs(cpu, not_v6_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_V6K)) { + define_arm_cp_regs(cpu, v6k_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_V7)) { define_arm_cp_regs(cpu, v7_cp_reginfo); } else { diff --git a/target-arm/translate.c b/target-arm/translate.c index a4429ea..e6b0d87 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2460,64 +2460,9 @@ static int cp15_user_ok(CPUARMState *env, uint32_t insn) } return 0; } - - if (cpn == 13 && cpm == 0) { - /* TLS register. */ - if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT))) - return 1; - } return 0; } -static int cp15_tls_load_store(CPUARMState *env, DisasContext *s, uint32_t insn, uint32_t rd) -{ - TCGv tmp; - int cpn = (insn >> 16) & 0xf; - int cpm = insn & 0xf; - int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38); - - if (!arm_feature(env, ARM_FEATURE_V6K)) - return 0; - - if (!(cpn == 13 && cpm == 0)) - return 0; - - if (insn & ARM_CP_RW_BIT) { - switch (op) { - case 2: - tmp = load_cpu_field(cp15.c13_tls1); - break; - case 3: - tmp = load_cpu_field(cp15.c13_tls2); - break; - case 4: - tmp = load_cpu_field(cp15.c13_tls3); - break; - default: - return 0; - } - store_reg(s, rd, tmp); - - } else { - tmp = load_reg(s, rd); - switch (op) { - case 2: - store_cpu_field(tmp, cp15.c13_tls1); - break; - case 3: - store_cpu_field(tmp, cp15.c13_tls2); - break; - case 4: - store_cpu_field(tmp, cp15.c13_tls3); - break; - default: - tcg_temp_free_i32(tmp); - return 0; - } - } - return 1; -} - /* Disassemble system coprocessor (cp15) instruction. Return nonzero if instruction is not defined. */ static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn) @@ -2548,9 +2493,6 @@ static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn) rd = (insn >> 12) & 0xf; - if (cp15_tls_load_store(env, s, insn, rd)) - return 0; - tmp2 = tcg_const_i32(insn); if (insn & ARM_CP_RW_BIT) { tmp = tcg_temp_new_i32();