From patchwork Mon May 14 19:03:17 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8612 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id B967823E61 for ; Mon, 14 May 2012 19:03:59 +0000 (UTC) Received: from mail-gg0-f180.google.com (mail-gg0-f180.google.com [209.85.161.180]) by fiordland.canonical.com (Postfix) with ESMTP id 88C4DA1806E for ; Mon, 14 May 2012 19:03:59 +0000 (UTC) Received: by mail-gg0-f180.google.com with SMTP id f1so3804944ggn.11 for ; Mon, 14 May 2012 12:03:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=qhJN8DqNNYgtKjyIIDCmY/AiKfcMiYRB5KKjaKNhz2U=; b=ThNhY3ychoZAjcXQnN121f5UzUIZZ02dIuVe3GD8/naCFQYNF036k8KMidqYUnhtj/ oVTsTnC02l4fz+kwFSOqdDAZvO4uOnwo2HeF0FWxJCeEZDNGb71RR0WLnaaFZKcmRpDO 74BL6hX24CYdlX5Yqxz1AwinOV0lW4cCjDyw1mZyosDT1tlHmNuq6yR7afPbL0oaj9G2 Vf9g80NfZWGU27c3JYyRGod/S4KKtUZpemuO00XEserTeKAN8XwlARBo0PQ96e6geNx6 z78PR9YfVdvhAbwV/IuwYHQWdNBnjNBVR7iajInl49zT3u5/DKs3XEWB9SQlXhBmyXS3 l7Vw== Received: by 10.50.185.233 with SMTP id ff9mr4917681igc.57.1337022239117; Mon, 14 May 2012 12:03:59 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.35.72 with SMTP id o8csp365951ibd; Mon, 14 May 2012 12:03:58 -0700 (PDT) Received: by 10.216.141.139 with SMTP id g11mr5768611wej.86.1337022237618; Mon, 14 May 2012 12:03:57 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id s7si8510631wek.71.2012.05.14.12.03.55 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 14 May 2012 12:03:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SU0YP-0005nO-JU; Mon, 14 May 2012 20:03:33 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rusty Russell Subject: [PATCH qom-next v2 18/33] target-arm: Convert cp15 crn=10 registers Date: Mon, 14 May 2012 20:03:17 +0100 Message-Id: <1337022212-22219-19-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> References: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQnD6VH6aND82/5lkMtSwjq3tOtwBMmezK9WpsaYjUTrc3ZmGI0fdhC66AHagygK0YfAKOfX We RAZ/WI the entire block of crn=10 registers. Note that this actually covers not just the implementation-defined TLB lockdown registers but also a number of v7 VMSA memory attribute registers which we would need to implement to support TEX remap. We retain the previous QEMU behaviour in this conversion, though. Signed-off-by: Peter Maydell --- target-arm/helper.c | 11 +++++------ 1 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index c19ba9e..e83f1c8 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -111,6 +111,11 @@ static const ARMCPRegInfo cp_reginfo[] = { { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse), .resetvalue = 0, .writefn = contextidr_write }, + /* ??? This covers not just the impdef TLB lockdown registers but also + * some v7VMSA registers relating to TEX remap, so it is overly broad. + */ + { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY, + .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, REGINFO_SENTINEL }; @@ -1800,9 +1805,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) goto bad_reg; } break; - case 10: /* MMU TLB lockdown. */ - /* ??? TLB lockdown not implemented. */ - break; case 12: /* Reserved. */ goto bad_reg; case 15: /* Implementation specific. */ @@ -2080,9 +2082,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) goto bad_reg; } break; - case 10: /* MMU TLB lockdown. */ - /* ??? TLB lockdown not implemented. */ - return 0; case 11: /* TCM DMA control. */ case 12: /* Reserved. */ goto bad_reg;