From patchwork Thu Jun 28 14:36:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 9678 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 1A7F323E23 for ; Thu, 28 Jun 2012 14:36:18 +0000 (UTC) Received: from mail-gh0-f180.google.com (mail-gh0-f180.google.com [209.85.160.180]) by fiordland.canonical.com (Postfix) with ESMTP id DF72EA18BCB for ; Thu, 28 Jun 2012 14:36:17 +0000 (UTC) Received: by ghbz12 with SMTP id z12so2079635ghb.11 for ; Thu, 28 Jun 2012 07:36:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=MocmpayJojnJMtxUZea0qayKG0XCfhCSOLNpSgNQvsQ=; b=Fb2Qlr7DVP+YQArquMKRIhxHWGZJQwDZp01ha554UdvIJrlXjXhw0IqZKFjPXg6CGP JTfisX+IVpWzC5eUkLuP22DkcYiVCN+b5HlOpoYs6WHpcH0hbxOkMNADjNdg3Z3ssoC7 hBui0P1yFdDmaVAn+gU5yE+e9I2REiqb5Al8/wWAPqRMwEqugUm6JzvQFYqnOKGvsQSw +KYtUofLqa7E568rtOJ3e82qezXlRN556RsiG1re4SzEt7M8xAX6qj4VGC98ViF0kxGI 7CXrgOupgyXjeNEhGsVh3/vhNiPHzSfCAlCqDeCNuHrUwxDb0XrwnCiVF8EeU3jTAdj6 mJYw== Received: by 10.50.40.193 with SMTP id z1mr202058igk.0.1340894177017; Thu, 28 Jun 2012 07:36:17 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp43446ibb; Thu, 28 Jun 2012 07:36:14 -0700 (PDT) Received: by 10.216.137.14 with SMTP id x14mr1161356wei.138.1340894173536; Thu, 28 Jun 2012 07:36:13 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id bb5si650544wib.34.2012.06.28.07.36.13 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 28 Jun 2012 07:36:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SkFpG-0008Me-RP; Thu, 28 Jun 2012 15:36:06 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 12/13] target-arm: Implement TTBCR changes for LPAE Date: Thu, 28 Jun 2012 15:36:05 +0100 Message-Id: <1340894166-32105-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1340894166-32105-1-git-send-email-peter.maydell@linaro.org> References: <1340894166-32105-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQn3J2t4+vKJleUAYtFBti3UueDg2TRfiF3Krb8OtFx5TZqY67GyTjvWRqfrLRvE9P75O2eO Implement the changes to the TTBCR register required for LPAE: * many fewer bits should be RAZ/WI * since TTBCR changes can result in a change of ASID, we must flush the TLB on writes to it Signed-off-by: Peter Maydell --- target-arm/helper.c | 15 ++++++++++++++- 1 files changed, 14 insertions(+), 1 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 55f9f8a..9ff0771 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -692,7 +692,20 @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] = { static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - value &= 7; + if (arm_feature(env, ARM_FEATURE_LPAE)) { + value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); + /* With LPAE the TTBCR could result in a change of ASID + * via the TTBCR.A1 bit, so do a TLB flush. + */ + tlb_flush(env, 1); + } else { + value &= 7; + } + /* Note that we always calculate c2_mask and c2_base_mask, but + * they are only used for short-descriptor tables (ie if EAE is 0); + * for long-descriptor tables the TTBCR fields are used differently + * and the c2_mask and c2_base_mask values are meaningless. + */ env->cp15.c2_control = value; env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> value); env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> value);