From patchwork Thu Jun 28 14:36:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 9680 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id E869923E23 for ; Thu, 28 Jun 2012 14:36:18 +0000 (UTC) Received: from mail-gh0-f180.google.com (mail-gh0-f180.google.com [209.85.160.180]) by fiordland.canonical.com (Postfix) with ESMTP id B7C91A18BCB for ; Thu, 28 Jun 2012 14:36:18 +0000 (UTC) Received: by mail-gh0-f180.google.com with SMTP id z12so2079625ghb.11 for ; Thu, 28 Jun 2012 07:36:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=lYQ6ddirEcOPdB+HMeYsB1HNdmIpqOGLYxX0MyQdhp8=; b=Z/Amjpw2RgcssHtBu3qITbPLA59P1B0uAfkviW7xaJLbG9kp3ZVUBkLrGm/4X4bED9 IZV5FAXXf/WP1YOvnpFmW+H4hNYN35452Nitz8gdjR2VzCAmt35UewQgGSdTgTdpu6dg Injs8NA1KUyFlHnaxmYM6LY/LIqvKdLHdbr0XeJqi7ydC/CzDugKm+37oRHZ+c8B0ybO WOm7Qy1uua3wS+fzkPwEAQMdzmzcPyGUMsIOtHZMZGYCa6ry+UozD4fyEU1EYUVyM6tv hEqWu5or0YcKbXlNKoKBt5XAQ+gITkgB7H2ZnF0guEo3TAT9z5++5/h7wBCIixhoXXXp wysg== Received: by 10.42.89.72 with SMTP id f8mr672245icm.33.1340894173859; Thu, 28 Jun 2012 07:36:13 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp43431ibb; Thu, 28 Jun 2012 07:36:11 -0700 (PDT) Received: by 10.204.148.72 with SMTP id o8mr1313607bkv.127.1340894170468; Thu, 28 Jun 2012 07:36:10 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id hg14si20575600bkc.42.2012.06.28.07.36.09 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 28 Jun 2012 07:36:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SkFpG-0008MU-Hb; Thu, 28 Jun 2012 15:36:06 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 07/13] target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers Date: Thu, 28 Jun 2012 15:36:00 +0100 Message-Id: <1340894166-32105-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1340894166-32105-1-git-send-email-peter.maydell@linaro.org> References: <1340894166-32105-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQmHsR2DiqlMWbpsPa4SKPFRY6czyNhbnAMWBvRUebwKJiKJJtmIxelvE4Fi9IWi/w1zkrKl Add implementations of the AMAIR0 and AMAIR1 LPAE Auxiliary Memory Attribute Indirection Registers. These are implementation defined and we choose to implement them as RAZ/WI, matching the Cortex-A7 and Cortex-A15. Signed-off-by: Peter Maydell --- target-arm/helper.c | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 6ef0b1d..3ee0555 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -871,6 +871,19 @@ static const ARMCPRegInfo mpidr_cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo lpae_cp_reginfo[] = { + /* NOP AMAIR0/1: the override is because these clash with tha rather + * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo. + */ + { .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE, + .resetvalue = 0 }, + { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE, + .resetvalue = 0 }, + REGINFO_SENTINEL +}; + static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { env->cp15.c1_sys = value; @@ -1016,6 +1029,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_MPIDR)) { define_arm_cp_regs(cpu, mpidr_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_LPAE)) { + define_arm_cp_regs(cpu, lpae_cp_reginfo); + } /* Slightly awkwardly, the OMAP and StrongARM cores need all of * cp15 crn=0 to be writes-ignored, whereas for other cores they should * be read-only (ie write causes UNDEF exception).