From patchwork Mon Jul 16 13:24:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 10012 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 4FE0923F2A for ; Mon, 16 Jul 2012 13:24:32 +0000 (UTC) Received: from mail-gg0-f180.google.com (mail-gg0-f180.google.com [209.85.161.180]) by fiordland.canonical.com (Postfix) with ESMTP id 206A3A188AE for ; Mon, 16 Jul 2012 13:24:32 +0000 (UTC) Received: by mail-gg0-f180.google.com with SMTP id f1so5363090ggn.11 for ; Mon, 16 Jul 2012 06:24:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=43TvcJStgljWeEtyEfXgWHSr+wP2es6kcu9ZzamA9Ok=; b=Mb0+lET7+sv/VQ6WZDxn2YJ3hT0fGkcecGlcLCc5bPqRWXaamyf0Rk3OAlvexrHB3F 63dWNU8t5H3gM4nFmiyz6t5vVoYRDz4Z4RP5+6r2Ou+sBd7XSNmCCe81qoA9iTLT7IVv /UE7TnGvi5kyPGM3plsUhuN1/BYk1oj7VROwS/jQN7Td5px6IXHBktWRPdQph/MrHrOu 0OSzzbEkeXbF4rCj01OqiBc/INstkh2TPLnwsxta6J/7V7dxYwWjl4ZXoqHH6paCO1U0 TsOzIOyqtCmHk2A0Xkl1XOC9qCkuYn66NP1lLN9leJuV6tsq0+nXWi4mu8qZbFfk4iXw fZ6w== Received: by 10.50.40.193 with SMTP id z1mr5257164igk.0.1342445071476; Mon, 16 Jul 2012 06:24:31 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.241.2 with SMTP id lc2csp7941ibb; Mon, 16 Jul 2012 06:24:30 -0700 (PDT) Received: by 10.180.78.33 with SMTP id y1mr18263191wiw.3.1342445070288; Mon, 16 Jul 2012 06:24:30 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id cb1si23877909wib.30.2012.07.16.06.24.29 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 16 Jul 2012 06:24:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SqlHd-0002Nq-A1; Mon, 16 Jul 2012 14:24:17 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Peter Crosthwaite Subject: [PATCH v2 5/6] hw/arm_boot.c: Support DTBs which use 64 bit addresses Date: Mon, 16 Jul 2012 14:24:15 +0100 Message-Id: <1342445056-9129-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1342445056-9129-1-git-send-email-peter.maydell@linaro.org> References: <1342445056-9129-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQk7ZrYrXx+9RkVR968mN+BuKM2Z73fUYW7mWjdTBd+dv18J++OAyuFDqmK5TWtt/yNpjeyn Support the case where the device tree blob specifies that #address-cells and #size-cells are greater than 1. (This is needed for device trees which can handle 64 bit physical addresses and thus total RAM sizes over 4GB.) Signed-off-by: Peter Maydell Reviewed-by: Peter A. G. Crosthwaite --- hw/arm_boot.c | 35 ++++++++++++++++++++++++++++++++--- 1 files changed, 32 insertions(+), 3 deletions(-) diff --git a/hw/arm_boot.c b/hw/arm_boot.c index af71ed6..a6e9143 100644 --- a/hw/arm_boot.c +++ b/hw/arm_boot.c @@ -216,11 +216,12 @@ static void set_kernel_args_old(const struct arm_boot_info *info) static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo) { #ifdef CONFIG_FDT - uint32_t mem_reg_property[] = { cpu_to_be32(binfo->loader_start), - cpu_to_be32(binfo->ram_size) }; + uint32_t *mem_reg_property; + uint32_t mem_reg_propsize; void *fdt = NULL; char *filename; int size, rc; + uint32_t acells, scells, hival; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); if (!filename) { @@ -236,8 +237,36 @@ static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo) } g_free(filename); + acells = qemu_devtree_getprop_cell(fdt, "/", "#address-cells"); + scells = qemu_devtree_getprop_cell(fdt, "/", "#size-cells"); + if (acells == 0 || scells == 0) { + fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); + return -1; + } + + mem_reg_propsize = acells + scells; + mem_reg_property = g_new0(uint32_t, mem_reg_propsize); + mem_reg_property[acells - 1] = cpu_to_be32(binfo->loader_start); + hival = cpu_to_be32(binfo->loader_start >> 32); + if (acells > 1) { + mem_reg_property[acells - 2] = hival; + } else if (hival != 0) { + fprintf(stderr, "qemu: dtb file not compatible with " + "RAM start address > 4GB\n"); + exit(1); + } + mem_reg_property[acells + scells - 1] = cpu_to_be32(binfo->ram_size); + hival = cpu_to_be32(binfo->ram_size >> 32); + if (scells > 1) { + mem_reg_property[acells + scells - 2] = hival; + } else if (hival != 0) { + fprintf(stderr, "qemu: dtb file not compatible with " + "RAM size > 4GB\n"); + exit(1); + } + rc = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, - sizeof(mem_reg_property)); + mem_reg_propsize * sizeof(uint32_t)); if (rc < 0) { fprintf(stderr, "couldn't set /memory/reg\n"); }