From patchwork Thu Oct 25 12:57:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12510 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 638B123EFB for ; Thu, 25 Oct 2012 12:57:53 +0000 (UTC) Received: from mail-ia0-f180.google.com (mail-ia0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 1A404A18FEB for ; Thu, 25 Oct 2012 12:57:52 +0000 (UTC) Received: by mail-ia0-f180.google.com with SMTP id f6so1219551iag.11 for ; Thu, 25 Oct 2012 05:57:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=G2c0d+p/trFQukatyX4F8Y+nFfzEzYLNju1xjdAG4MU=; b=httu/4k1WeYIlIDAwteY5dp5K2GABcnpe4/EWjw9mlHFgEdsq9QR9LsKkeuKuz60HS Wi61tcHeKpBwY3znqiyo1kpnWsGO+IxlNHYbE+3mbGgaAEVQO5exe2GsckTutUJ+xqmH 5Tc58Mz+5ujTWSQ0G9ByjEgKsyZC+PKPLvzRxG+9gRMhOsppQjNvWr33nucvzxTiBHed XZ07su3d3BOotQz/zVxl+fedEvo90GyloSoGg6o2rZ3Z+Xb6hD9Baw1jkzcAvx8QXJWw LdIjrXIBdHEFQGH+JOSRPEooaoT9YzydKekMO1y2addMbTbIRlH5Hce1aAl/LHjIzZNB HE6g== Received: by 10.50.140.97 with SMTP id rf1mr4225814igb.70.1351169872800; Thu, 25 Oct 2012 05:57:52 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp42919igt; Thu, 25 Oct 2012 05:57:51 -0700 (PDT) Received: by 10.180.87.74 with SMTP id v10mr13661170wiz.21.1351169871313; Thu, 25 Oct 2012 05:57:51 -0700 (PDT) Received: from mnementh.archaic.org.uk (1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id l2si5562769wiz.18.2012.10.25.05.57.50 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 25 Oct 2012 05:57:51 -0700 (PDT) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1TRN0N-0001Qr-ST; Thu, 25 Oct 2012 13:57:47 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 08/12] hw/arm_timer: Use LOG_GUEST_ERROR and LOG_UNIMP Date: Thu, 25 Oct 2012 13:57:43 +0100 Message-Id: <1351169867-5466-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1351169867-5466-1-git-send-email-peter.maydell@linaro.org> References: <1351169867-5466-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQn8FFzL0tI/XljupMqoudbwGray5s0ZSDalM8b9o4/04Wef8pM8d47MwfFwnqjwF+FDiqQS Use LOG_GUEST_ERROR to report guest accesses to bad register offsets, and LOG_UNIMP for access to the unimplemented test registers. Signed-off-by: Peter Maydell --- hw/arm_timer.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/hw/arm_timer.c b/hw/arm_timer.c index 2e13621..af339d3 100644 --- a/hw/arm_timer.c +++ b/hw/arm_timer.c @@ -64,7 +64,8 @@ static uint32_t arm_timer_read(void *opaque, hwaddr offset) return 0; return s->int_level; default: - hw_error("%s: Bad offset %x\n", __func__, (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset %x\n", __func__, (int)offset); return 0; } } @@ -131,7 +132,8 @@ static void arm_timer_write(void *opaque, hwaddr offset, arm_timer_recalibrate(s, 0); break; default: - hw_error("%s: Bad offset %x\n", __func__, (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset %x\n", __func__, (int)offset); } arm_timer_update(s); } @@ -223,10 +225,14 @@ static uint64_t sp804_read(void *opaque, hwaddr offset, /* Integration Test control registers, which we won't support */ case 0xf00: /* TimerITCR */ case 0xf04: /* TimerITOP (strictly write only but..) */ + qemu_log_mask(LOG_UNIMP, + "%s: integration test registers unimplemented\n", + __func__); return 0; } - hw_error("%s: Bad offset %x\n", __func__, (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset %x\n", __func__, (int)offset); return 0; } @@ -246,7 +252,8 @@ static void sp804_write(void *opaque, hwaddr offset, } /* Technically we could be writing to the Test Registers, but not likely */ - hw_error("%s: Bad offset %x\n", __func__, (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n", + __func__, (int)offset); } static const MemoryRegionOps sp804_ops = { @@ -300,7 +307,7 @@ static uint64_t icp_pit_read(void *opaque, hwaddr offset, /* ??? Don't know the PrimeCell ID for this device. */ n = offset >> 8; if (n > 2) { - hw_error("%s: Bad timer %d\n", __func__, n); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); } return arm_timer_read(s->timer[n], offset & 0xff); @@ -314,7 +321,7 @@ static void icp_pit_write(void *opaque, hwaddr offset, n = offset >> 8; if (n > 2) { - hw_error("%s: Bad timer %d\n", __func__, n); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); } arm_timer_write(s->timer[n], offset & 0xff, value);