From patchwork Tue Nov 20 13:31:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12996 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id E05CA23FC0 for ; Tue, 20 Nov 2012 13:54:52 +0000 (UTC) Received: from mail-ie0-f180.google.com (mail-ie0-f180.google.com [209.85.223.180]) by fiordland.canonical.com (Postfix) with ESMTP id 79609A1894A for ; Tue, 20 Nov 2012 13:54:52 +0000 (UTC) Received: by mail-ie0-f180.google.com with SMTP id e10so8168505iej.11 for ; Tue, 20 Nov 2012 05:54:52 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=Fgb4xfSEuejP8UNTTVRTMgWrmFT6ySNdAnQ8csowCG8=; b=KQeeiSaxycy5ASazawFYqM6Rurz7TkPQO8la/q+cWWmRRaBxPZNoLy11q9t4HZPnu0 cmhkumGqMW1RGELZq77m1mD5QLjTm5vlRg1IWH6eS+6n3sOHz6SsrYHKslN9kwiv8Css EBvOuWFmVrrt5TDsVAZ5w3PIWQWLy7JGxeqTTRxRCfyYdjlUYW/Lq2Nf+T4kAcNCWVI2 fJz/kNqgFhowZblPQqrgYQb7+s+Po7iMCyvhHDtY7bNxry4eSDlljSgAdVHRDIangx4i eJUYaERJGP2hPqpkTYuATMsjrCxEqkxlL44nkDZUtTQHzbnotkDvj+5INz9D9zP/2cx3 Z0BQ== Received: by 10.50.173.34 with SMTP id bh2mr9920726igc.70.1353419690783; Tue, 20 Nov 2012 05:54:50 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp320853igt; Tue, 20 Nov 2012 05:54:49 -0800 (PST) Received: by 10.180.89.234 with SMTP id br10mr14614886wib.2.1353419689233; Tue, 20 Nov 2012 05:54:49 -0800 (PST) Received: from mnementh.archaic.org.uk (1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id n7si7054101wen.110.2012.11.20.05.54.48 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 20 Nov 2012 05:54:49 -0800 (PST) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1Tanuw-0006Di-Qt; Tue, 20 Nov 2012 13:31:10 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, patches@linaro.org, Blue Swirl , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Avi Kivity , Marcelo Tosatti Subject: [RFC v4 3/8] ARM KVM: save and load VFP registers from kernel Date: Tue, 20 Nov 2012 13:31:05 +0000 Message-Id: <1353418270-23881-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1353418270-23881-1-git-send-email-peter.maydell@linaro.org> References: <1353418270-23881-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQniddHtnNIzZvR33ddv6uwYb8q6lZmPAylOWFGpOEEtxHlonECPuqbZS1MXZdQluMsq13H6 Add support for saving and restoring VFP register state from the kernel. This includes a check that the KVM-created CPU has full VFP support (as the TCG Cortex-A15 model always does), since for the moment ARM QEMU doesn't have any way to tweak optional features on created CPUs. Signed-off-by: Peter Maydell --- target-arm/kvm.c | 78 +++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 75 insertions(+), 3 deletions(-) diff --git a/target-arm/kvm.c b/target-arm/kvm.c index 8e4b989..4217ad6 100644 --- a/target-arm/kvm.c +++ b/target-arm/kvm.c @@ -38,10 +38,28 @@ int kvm_arch_init(KVMState *s) int kvm_arch_init_vcpu(CPUARMState *env) { struct kvm_vcpu_init init; + int ret; + uint64_t v; + struct kvm_one_reg r; init.target = KVM_ARM_TARGET_CORTEX_A15; memset(init.features, 0, sizeof(init.features)); - return kvm_vcpu_ioctl(env, KVM_ARM_VCPU_INIT, &init); + ret = kvm_vcpu_ioctl(env, KVM_ARM_VCPU_INIT, &init); + if (ret) { + return ret; + } + /* Query the kernel to make sure it supports 32 VFP + * registers: QEMU's "cortex-a15" CPU is always a + * VFP-D32 core. The simplest way to do this is just + * to attempt to read register d31. + */ + r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31; + r.addr = (uintptr_t)(&v); + ret = kvm_vcpu_ioctl(env, KVM_GET_ONE_REG, &r); + if (ret == ENOENT) { + return EINVAL; + } + return ret; } typedef struct Reg { @@ -67,6 +85,13 @@ typedef struct Reg { offsetof(CPUARMState, QEMUFIELD) \ } +#define VFPSYSREG(R) \ + { \ + KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \ + KVM_REG_ARM_VFP_##R, \ + offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R]) \ + } + static const Reg regs[] = { /* R0_usr .. R14_usr */ COREREG(usr_regs.uregs[0], regs[0]), @@ -114,6 +139,13 @@ static const Reg regs[] = { CP15REG(1, 0, 0, 0, cp15.c1_sys), /* SCTLR */ CP15REG(2, 0, 0, 2, cp15.c2_control), /* TTBCR */ CP15REG(3, 0, 0, 0, cp15.c3), /* DACR */ + /* VFP system registers */ + VFPSYSREG(FPSID), + VFPSYSREG(MVFR1), + VFPSYSREG(MVFR0), + VFPSYSREG(FPEXC), + VFPSYSREG(FPINST), + VFPSYSREG(FPINST2), }; int kvm_arch_put_registers(CPUARMState *env, int level) @@ -121,7 +153,7 @@ int kvm_arch_put_registers(CPUARMState *env, int level) struct kvm_one_reg r; int mode, bn; int ret, i; - uint32_t cpsr; + uint32_t cpsr, fpscr; uint64_t ttbr; /* Make sure the banked regs are properly set */ @@ -172,6 +204,26 @@ int kvm_arch_put_registers(CPUARMState *env, int level) (2 << KVM_REG_ARM_CRM_SHIFT) | (1 << KVM_REG_ARM_OPC1_SHIFT); r.addr = (uintptr_t)(&ttbr); ret = kvm_vcpu_ioctl(env, KVM_SET_ONE_REG, &r); + if (ret) { + return ret; + } + + /* VFP registers */ + r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; + for (i = 0; i < 32; i++) { + r.addr = (uintptr_t)(&env->vfp.regs[i]); + ret = kvm_vcpu_ioctl(env, KVM_SET_ONE_REG, &r); + if (ret) { + return ret; + } + r.id++; + } + + r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | + KVM_REG_ARM_VFP_FPSCR; + fpscr = vfp_get_fpscr(env); + r.addr = (uintptr_t)&fpscr; + ret = kvm_vcpu_ioctl(env, KVM_SET_ONE_REG, &r); return ret; } @@ -181,7 +233,7 @@ int kvm_arch_get_registers(CPUARMState *env) struct kvm_one_reg r; int mode, bn; int ret, i; - uint32_t cpsr; + uint32_t cpsr, fpscr; uint64_t ttbr; for (i = 0; i < ARRAY_SIZE(regs); i++) { @@ -246,6 +298,26 @@ int kvm_arch_get_registers(CPUARMState *env) env->cp15.c2_mask = ~(0xffffffffu >> env->cp15.c2_control); env->cp15.c2_base_mask = ~(0x3fffu >> env->cp15.c2_control); + /* VFP registers */ + r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; + for (i = 0; i < 32; i++) { + r.addr = (uintptr_t)(&env->vfp.regs[i]); + ret = kvm_vcpu_ioctl(env, KVM_GET_ONE_REG, &r); + if (ret) { + return ret; + } + r.id++; + } + + r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | + KVM_REG_ARM_VFP_FPSCR; + r.addr = (uintptr_t)&fpscr; + ret = kvm_vcpu_ioctl(env, KVM_GET_ONE_REG, &r); + if (ret) { + return ret; + } + vfp_set_fpscr(env, fpscr); + return 0; }