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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id hl1si3622795wjb.105.2013.03.24.04.32.54 (version=TLSv1 cipher=RC4-SHA bits=128/128); Sun, 24 Mar 2013 04:32:54 -0700 (PDT) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1UJjAG-0001W3-8l; Sun, 24 Mar 2013 11:32:40 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , "Michael S. Tsirkin" , Paul Brook , Arnd Bergmann , Will Deacon Subject: [PATCH 05/10] versatile_pci: Use separate PCI I/O space rather than system I/O space Date: Sun, 24 Mar 2013 11:32:35 +0000 Message-Id: <1364124760-5794-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1364124760-5794-1-git-send-email-peter.maydell@linaro.org> References: <1364124760-5794-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQmSZQVUTtwfFYKdlE17XO4Lexk+FglgC48KVruIj93TC2NOkDh+lFCFAIeB2tzYZ0HP0Egj Rather than overloading the system I/O space (which doesn't even make any sense on ARM) for PCI I/O, create an memory region in the PCI controller and use that to represent the I/O space. Signed-off-by: Peter Maydell --- hw/versatile_pci.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c index dfd3001..777e9b1 100644 --- a/hw/versatile_pci.c +++ b/hw/versatile_pci.c @@ -19,7 +19,8 @@ typedef struct { qemu_irq irq[4]; MemoryRegion mem_config; MemoryRegion mem_config2; - MemoryRegion isa; + MemoryRegion pci_io_space; + MemoryRegion pci_io_window; PCIBus pci_bus; PCIDevice pci_dev; @@ -77,8 +78,10 @@ static void pci_vpb_init(Object *obj) PCIHostState *h = PCI_HOST_BRIDGE(obj); PCIVPBState *s = PCI_VPB(obj); + memory_region_init(&s->pci_io_space, "pci_io", 1ULL << 32); + pci_bus_new_inplace(&s->pci_bus, DEVICE(obj), "pci", - get_system_memory(), get_system_io(), + get_system_memory(), &s->pci_io_space, PCI_DEVFN(11, 0)); h->bus = &s->pci_bus; @@ -111,8 +114,14 @@ static void pci_vpb_realize(DeviceState *dev, Error **errp) memory_region_init_io(&s->mem_config2, &pci_vpb_config_ops, &s->pci_bus, "pci-vpb-config", 0x1000000); sysbus_init_mmio(sbd, &s->mem_config2); - isa_mmio_setup(&s->isa, 0x0100000); - sysbus_init_mmio(sbd, &s->isa); + + /* The window into I/O space is always into a fixed base address; + * its size is the same for both realview and versatile. + */ + memory_region_init_alias(&s->pci_io_window, "pci-vbp-io-window", + &s->pci_io_space, 0, 0x100000); + + sysbus_init_mmio(sbd, &s->pci_io_space); /* TODO Remove once realize propagates to child devices. */ object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);