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[81.2.115.146]) by mx.google.com with ESMTPS id ml5si2960228lbc.5.2014.01.26.11.25.17 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sun, 26 Jan 2014 11:25:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1W7VKU-0005hG-3N; Sun, 26 Jan 2014 19:25:14 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexander Graf , Michael Matz , Claudio Fontana , Dirk Mueller , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Christoffer Dall , Will Newton , Peter Crosthwaite Subject: [PATCH 21/21] target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group Date: Sun, 26 Jan 2014 19:25:12 +0000 Message-Id: <1390764312-21789-22-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1390764312-21789-1-git-send-email-peter.maydell@linaro.org> References: <1390764312-21789-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add the SIMD FNEG and FABS instructions in the SIMD 2-reg-misc group. Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index db89327..797e364 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -6247,7 +6247,7 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u, { /* Handle 64->64 opcodes which are shared between the scalar and * vector 2-reg-misc groups. We cover every integer opcode where size == 3 - * is valid in either group. + * is valid in either group and also the double-precision fp ops. */ TCGCond cond; @@ -6285,6 +6285,12 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u, tcg_temp_free_i64(tcg_zero); } break; + case 0x2f: /* FABS */ + gen_helper_vfp_absd(tcg_rd, tcg_rn); + break; + case 0x6f: /* FNEG */ + gen_helper_vfp_negd(tcg_rd, tcg_rn); + break; default: g_assert_not_reached(); } @@ -7604,6 +7610,13 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) opcode |= (extract32(size, 1, 1) << 5) | (u << 6); size = extract32(size, 0, 1) ? 3 : 2; switch (opcode) { + case 0x2f: /* FABS */ + case 0x6f: /* FNEG */ + if (size == 3 && !is_q) { + unallocated_encoding(s); + return; + } + break; case 0x16: /* FCVTN, FCVTN2 */ case 0x17: /* FCVTL, FCVTL2 */ case 0x18: /* FRINTN */ @@ -7615,7 +7628,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) case 0x2c: /* FCMGT (zero) */ case 0x2d: /* FCMEQ (zero) */ case 0x2e: /* FCMLT (zero) */ - case 0x2f: /* FABS */ case 0x38: /* FRINTP */ case 0x39: /* FRINTZ */ case 0x3a: /* FCVTPS */ @@ -7631,7 +7643,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) case 0x5d: /* UCVTF */ case 0x6c: /* FCMGE (zero) */ case 0x6d: /* FCMLE (zero) */ - case 0x6f: /* FNEG */ case 0x79: /* FRINTI */ case 0x7a: /* FCVTPU */ case 0x7b: /* FCVTZU */ @@ -7708,6 +7719,12 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) tcg_temp_free_i32(tcg_zero); } break; + case 0x2f: /* FABS */ + gen_helper_vfp_abss(tcg_res, tcg_op); + break; + case 0x6f: /* FNEG */ + gen_helper_vfp_negs(tcg_res, tcg_op); + break; default: g_assert_not_reached(); }