From patchwork Sat Feb 15 16:07:09 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 24684 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ie0-f198.google.com (mail-ie0-f198.google.com [209.85.223.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 273612127C for ; Sat, 15 Feb 2014 16:07:39 +0000 (UTC) Received: by mail-ie0-f198.google.com with SMTP id at1sf15523522iec.1 for ; Sat, 15 Feb 2014 08:07:38 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=Wya9lOJhmLSLmfzK+1VUizF8SLvAIkgKcttcmYDY9bA=; b=KcLricusFem71yZadb45WT+VuSxyJfU20neA/8hwa4ZtHTKdxWs44oDLDDs71DZl9d Jb3eKJock4yB7l9Y2AEx03l/B53W0LFDkWJyH+orJIfp+BZWJaic30F39Q3qHXgon89W Y/Hj9aowtwORBO7RTt/quPY865z6Y1hgFxISNhMcdxL/Z8PpM9NrpOL9iF01mMbHHMxD 9k3+NqaJF+pG6QMDsqPWBofKBZ3g/nYmDjv+tbKpqwUN4horBofWnibTKPQZx/cPDUDc BsSiCH81L3V5L12sfiNtHg2fRGJmzBrJ/YbyA7RpgY7F68MYkuc7z3aLW+jQZ6KAB06q UXkA== X-Gm-Message-State: ALoCoQng6aTjyCDYlwlbv8SFTOL6HG+O62g0Ky4SRaP9Axl5HjaqCZt72YnCh40wr4ajAtFV+Nr9 X-Received: by 10.182.19.231 with SMTP id i7mr6307311obe.25.1392480458335; Sat, 15 Feb 2014 08:07:38 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.109.101 with SMTP id k92ls359905qgf.78.gmail; Sat, 15 Feb 2014 08:07:38 -0800 (PST) X-Received: by 10.52.156.232 with SMTP id wh8mr5032486vdb.23.1392480458166; Sat, 15 Feb 2014 08:07:38 -0800 (PST) Received: from mail-ve0-f173.google.com (mail-ve0-f173.google.com [209.85.128.173]) by mx.google.com with ESMTPS id eo4si2997754vdb.82.2014.02.15.08.07.38 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 15 Feb 2014 08:07:38 -0800 (PST) Received-SPF: neutral (google.com: 209.85.128.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.173; Received: by mail-ve0-f173.google.com with SMTP id jw12so3375659veb.4 for ; Sat, 15 Feb 2014 08:07:38 -0800 (PST) X-Received: by 10.52.166.103 with SMTP id zf7mr4618600vdb.30.1392480458088; Sat, 15 Feb 2014 08:07:38 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp25550vcz; Sat, 15 Feb 2014 08:07:37 -0800 (PST) X-Received: by 10.153.9.97 with SMTP id dr1mr2187001lad.45.1392480452492; Sat, 15 Feb 2014 08:07:32 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id n3si14728014lae.19.2014.02.15.08.07.29 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sat, 15 Feb 2014 08:07:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WEhm1-0006fq-Gv; Sat, 15 Feb 2014 16:07:25 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexander Graf , Michael Matz , Claudio Fontana , Dirk Mueller , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Christoffer Dall , Will Newton , Peter Crosthwaite , Rob Herring Subject: [PATCH v3 16/31] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers Date: Sat, 15 Feb 2014 16:07:09 +0000 Message-Id: <1392480444-25565-17-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1392480444-25565-1-git-send-email-peter.maydell@linaro.org> References: <1392480444-25565-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , In AArch64 the breakpoint and watchpoint registers are mandatory, so the kernel always accesses them on bootup. Implement dummy versions, which read as written but have no actual effect. Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite --- target-arm/cpu.h | 4 ++++ target-arm/helper.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 48419ae..db74ab7 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -216,6 +216,10 @@ typedef struct CPUARMState { uint32_t c15_diagnostic; /* diagnostic register */ uint32_t c15_power_diagnostic; uint32_t c15_power_control; /* power control */ + uint64_t dbgbvr[16]; /* breakpoint value registers */ + uint64_t dbgbcr[16]; /* breakpoint control registers */ + uint64_t dbgwvr[16]; /* watchpoint value registers */ + uint64_t dbgwcr[16]; /* watchpoint control registers */ } cp15; struct { diff --git a/target-arm/helper.c b/target-arm/helper.c index 0b2be71..0eb56ae 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1761,6 +1761,37 @@ static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri) return CP_ACCESS_OK; } +static void define_aarch64_debug_regs(ARMCPU *cpu) +{ + /* Define breakpoint and watchpoint registers. These do nothing + * but read as written, for now. + */ + int i; + + for (i = 0; i < 16; i++) { + ARMCPRegInfo dbgregs[] = { + { .name = "DBGBVR", .state = ARM_CP_STATE_AA64, + .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]) }, + { .name = "DBGBCR", .state = ARM_CP_STATE_AA64, + .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) }, + { .name = "DBGWVR", .state = ARM_CP_STATE_AA64, + .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]) }, + { .name = "DBGWCR", .state = ARM_CP_STATE_AA64, + .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]) }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, dbgregs); + } +} + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -1902,6 +1933,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) }; define_arm_cp_regs(cpu, v8_idregs); define_arm_cp_regs(cpu, v8_cp_reginfo); + define_aarch64_debug_regs(cpu); } if (arm_feature(env, ARM_FEATURE_MPU)) { /* These are the MPU registers prior to PMSAv6. Any new