From patchwork Mon Mar 17 22:12:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 26423 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qa0-f72.google.com (mail-qa0-f72.google.com [209.85.216.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id B410A202FA for ; Mon, 17 Mar 2014 22:16:36 +0000 (UTC) Received: by mail-qa0-f72.google.com with SMTP id f11sf13352720qae.11 for ; Mon, 17 Mar 2014 15:16:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:mime-version:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list:content-type :content-transfer-encoding; bh=Xjd6zx5iuq2/RWVIppEScFdoD1EOfwzpuA63avjIHXA=; b=lwiHTX6UjJndmuVF1+lTWBFTzPijN1U3qReHQk5vj1CViHaRWfBg82oECgFHXW8BgQ sLX24Ou44hKWyHr9qYpsLEJL0s4/a1ThxKEhwtMiYrJ+Vb5avWTBTjVnjMyXlRubUuep CJcQx0XWo3KnVOXPMw11kucQ7CXbehOJygiwoqxrfb9dYj4OR4ANMuv8JOxiYqcy4Tj4 sBJ47+DliLT+Oh9eMapg0ebzu3lCiTHW70aDpwSP4wxA2bLgCb7qQG2itQzou8rNUlqF p3jBv1edkJqylugRXZk9X9pKNu3V3aRWdwIZpj8AmolIWg+OH6qZj14DaxvwiQc9MoFr DVlA== X-Gm-Message-State: ALoCoQlHJA0ijom2J4WoBbt36uqWFQ0Hmh+9AToCeaIvZj5dBnYgRPxVGyM8fxeW8RGHHnJRRU6g X-Received: by 10.58.59.104 with SMTP id y8mr589324veq.18.1395094596491; Mon, 17 Mar 2014 15:16:36 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.97.70 with SMTP id l64ls1714913qge.16.gmail; Mon, 17 Mar 2014 15:16:36 -0700 (PDT) X-Received: by 10.58.112.98 with SMTP id ip2mr399974veb.35.1395094596380; Mon, 17 Mar 2014 15:16:36 -0700 (PDT) Received: from mail-vc0-f172.google.com (mail-vc0-f172.google.com [209.85.220.172]) by mx.google.com with ESMTPS id wm4si5789728vcb.79.2014.03.17.15.16.36 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 17 Mar 2014 15:16:36 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.172 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.172; Received: by mail-vc0-f172.google.com with SMTP id la4so6343692vcb.17 for ; Mon, 17 Mar 2014 15:16:36 -0700 (PDT) X-Received: by 10.58.90.99 with SMTP id bv3mr411122veb.34.1395094596284; Mon, 17 Mar 2014 15:16:36 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.78.9 with SMTP id i9csp159443vck; Mon, 17 Mar 2014 15:16:35 -0700 (PDT) X-Received: by 10.224.50.72 with SMTP id y8mr32205167qaf.36.1395094595658; Mon, 17 Mar 2014 15:16:35 -0700 (PDT) Received: from lists.gnu.org (lists.gnu.org. [208.118.235.17]) by mx.google.com with ESMTPS id y4si9505173qad.73.2014.03.17.15.16.35 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 17 Mar 2014 15:16:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Received: from localhost ([::1]:60588 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPfpj-0000SM-8b for patch@linaro.org; Mon, 17 Mar 2014 18:16:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51109) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPfmI-0004TJ-1T for qemu-devel@nongnu.org; Mon, 17 Mar 2014 18:13:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WPfmG-0007QW-OF for qemu-devel@nongnu.org; Mon, 17 Mar 2014 18:13:01 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:46921) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPfmG-0007Pr-GB for qemu-devel@nongnu.org; Mon, 17 Mar 2014 18:13:00 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WPfle-00054v-I9; Mon, 17 Mar 2014 22:12:22 +0000 From: Peter Maydell To: Anthony Liguori Date: Mon, 17 Mar 2014 22:12:18 +0000 Message-Id: <1395094341-19339-28-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1395094341-19339-1-git-send-email-peter.maydell@linaro.org> References: <1395094341-19339-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: Blue Swirl , =?UTF-8?q?Andreas=20F=C3=A4rber?= , qemu-devel@nongnu.org, Aurelien Jarno Subject: [Qemu-devel] [PULL 27/30] target-arm: A64: Implement scalar saturating narrow ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.172 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Alex Bennée This completes the set of integer narrowing saturating ops including: SQXTN, SQXTN2 SQXTUN, SQXTUN2 UQXTN, UQXTN2 Signed-off-by: Alex Bennée Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 1394822294-14837-23-git-send-email-peter.maydell@linaro.org --- target-arm/translate-a64.c | 35 ++++++++++++++++++++++++++++------- 1 file changed, 28 insertions(+), 7 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index d88ebe2..5f4c6bf 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -7200,7 +7200,8 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode, tcg_temp_free_ptr(fpst); } -static void handle_2misc_narrow(DisasContext *s, int opcode, bool u, bool is_q, +static void handle_2misc_narrow(DisasContext *s, bool scalar, + int opcode, bool u, bool is_q, int size, int rn, int rd) { /* Handle 2-reg-misc ops which are narrowing (so each 2*size element @@ -7209,13 +7210,22 @@ static void handle_2misc_narrow(DisasContext *s, int opcode, bool u, bool is_q, int pass; TCGv_i32 tcg_res[2]; int destelt = is_q ? 2 : 0; + int passes = scalar ? 1 : 2; - for (pass = 0; pass < 2; pass++) { + if (scalar) { + tcg_res[1] = tcg_const_i32(0); + } + + for (pass = 0; pass < passes; pass++) { TCGv_i64 tcg_op = tcg_temp_new_i64(); NeonGenNarrowFn *genfn = NULL; NeonGenNarrowEnvFn *genenvfn = NULL; - read_vec_element(s, tcg_op, rn, pass, MO_64); + if (scalar) { + read_vec_element(s, tcg_op, rn, pass, size + 1); + } else { + read_vec_element(s, tcg_op, rn, pass, MO_64); + } tcg_res[pass] = tcg_temp_new_i32(); switch (opcode) { @@ -7323,6 +7333,19 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) return; } break; + case 0x12: /* SQXTUN */ + if (u) { + unallocated_encoding(s); + return; + } + /* fall through */ + case 0x14: /* SQXTN, UQXTN */ + if (size == 3) { + unallocated_encoding(s); + return; + } + handle_2misc_narrow(s, true, opcode, u, false, size, rn, rd); + return; case 0xc ... 0xf: case 0x16 ... 0x1d: case 0x1f: @@ -7379,8 +7402,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) default: /* Other categories of encoding in this class: * + SUQADD/USQADD/SQABS/SQNEG : size 8, 16, 32 or 64 - * + SQXTN/SQXTN2/SQXTUN/SQXTUN2/UQXTN/UQXTN2: - * narrowing saturate ops: size 64/32/16 -> 32/16/8 */ unsupported_encoding(s, insn); return; @@ -9096,7 +9117,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) unallocated_encoding(s); return; } - handle_2misc_narrow(s, opcode, u, is_q, size, rn, rd); + handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd); return; case 0x4: /* CLS, CLZ */ if (size == 3) { @@ -9227,7 +9248,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) /* handle_2misc_narrow does a 2*size -> size operation, but these * instructions encode the source size rather than dest size. */ - handle_2misc_narrow(s, opcode, 0, is_q, size - 1, rn, rd); + handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd); return; case 0x17: /* FCVTL, FCVTL2 */ handle_2misc_widening(s, opcode, is_q, size, rn, rd);