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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id d69si9517870qga.80.2014.03.17.15.23.07 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 17 Mar 2014 15:23:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:60665 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPfw3-000820-9M for patch@linaro.org; Mon, 17 Mar 2014 18:23:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51311) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPfmO-0004ev-Da for qemu-devel@nongnu.org; Mon, 17 Mar 2014 18:13:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WPfmN-0007cf-8A for qemu-devel@nongnu.org; Mon, 17 Mar 2014 18:13:08 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:46921) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPfmN-0007Pr-1z for qemu-devel@nongnu.org; Mon, 17 Mar 2014 18:13:07 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WPfld-00052h-Db; Mon, 17 Mar 2014 22:12:21 +0000 From: Peter Maydell To: Anthony Liguori Date: Mon, 17 Mar 2014 22:11:56 +0000 Message-Id: <1395094341-19339-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1395094341-19339-1-git-send-email-peter.maydell@linaro.org> References: <1395094341-19339-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: Blue Swirl , =?UTF-8?q?Andreas=20F=C3=A4rber?= , qemu-devel@nongnu.org, Aurelien Jarno Subject: [Qemu-devel] [PULL 05/30] target-arm: Add ARM_CP_IO notation to PMCR reginfo X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Now that the PMCR writefn makes timer accesses, its reginfo needs the ARM_CP_IO flag, so that icount mode works correctly. (Fixes the bug accidentally introduced in commit 7c2cb42b). Reported-by: Laurent Desnogues Signed-off-by: Peter Maydell Message-id: 1394908291-16546-1-git-send-email-peter.maydell@linaro.org --- target-arm/helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index f0a1fd4..5080372 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1983,6 +1983,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo pmcr = { .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000, + .type = ARM_CP_IO, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), .accessfn = pmreg_access, .writefn = pmcr_write, .raw_writefn = raw_write,