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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id q1si12687327qab.31.2014.03.19.05.27.54 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 19 Mar 2014 05:27:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:40785 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WQFb8-0003hI-FW for patch@linaro.org; Wed, 19 Mar 2014 08:27:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55733) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WQFaH-0002mn-Qo for qemu-devel@nongnu.org; Wed, 19 Mar 2014 08:27:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WQFaC-0004j3-Bm for qemu-devel@nongnu.org; Wed, 19 Mar 2014 08:27:01 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:47074) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WQFaC-0004ie-5n for qemu-devel@nongnu.org; Wed, 19 Mar 2014 08:26:56 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WQFFj-0005to-32; Wed, 19 Mar 2014 12:05:47 +0000 From: Peter Maydell To: Anthony Liguori Date: Wed, 19 Mar 2014 12:05:42 +0000 Message-Id: <1395230746-22643-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1395230746-22643-1-git-send-email-peter.maydell@linaro.org> References: <1395230746-22643-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: Blue Swirl , =?UTF-8?q?Andreas=20F=C3=A4rber?= , qemu-devel@nongnu.org, Aurelien Jarno Subject: [Qemu-devel] [PULL 2/6] pl011: reset the fifo when enabled or disabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.177 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Rob Herring Intermittent issues have been seen where no serial input occurs. It appears the pl011 gets in a state where the rx interrupt never fires because the rx interrupt only asserts when crossing the fifo trigger level. The fifo state appears to get out of sync when the pl011 is re-configured. This combined with the rx timeout interrupt not being modeled results in no more rx interrupts. Disabling the fifo is the recommended way to clear the tx fifo in the TRM (section 3.3.8). The behavior in this case for the rx fifo is undefined in the TRM, but having fifo contents to be maintained during configuration changes is not likely expected behavior. Reseting the fifo state when the fifo size is changed is the simplest solution. Signed-off-by: Rob Herring Reviewed-by: Peter Maydell Message-id: 1395166721-15716-2-git-send-email-robherring2@gmail.com Signed-off-by: Peter Maydell --- hw/char/pl011.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index a8ae6f4..8103e2e 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -162,6 +162,11 @@ static void pl011_write(void *opaque, hwaddr offset, s->fbrd = value; break; case 11: /* UARTLCR_H */ + /* Reset the FIFO state on FIFO enable or disable */ + if ((s->lcr ^ value) & 0x10) { + s->read_count = 0; + s->read_pos = 0; + } s->lcr = value; pl011_set_read_trigger(s); break;