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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id dj6si3510194bkc.296.2014.03.28.09.27.04 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 28 Mar 2014 09:27:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WTZMP-0000cG-LR; Fri, 28 Mar 2014 16:10:25 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexander Graf , Michael Matz , Dirk Mueller , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Christoffer Dall , Will Newton , Peter Crosthwaite Subject: [PATCH v5 20/37] target-arm: Implement ARMv8 MVFR registers Date: Fri, 28 Mar 2014 16:10:07 +0000 Message-Id: <1396023024-2262-21-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1396023024-2262-1-git-send-email-peter.maydell@linaro.org> References: <1396023024-2262-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.171 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , For ARMv8 there are two changes to the MVFR media feature registers: * there is a new MVFR2 which is accessible from 32 bit code * 64 bit code accesses these via the usual sysreg instructions rather than with a floating-point specific instruction Implement this. Signed-off-by: Peter Maydell --- target-arm/cpu-qom.h | 1 + target-arm/cpu.c | 1 + target-arm/cpu.h | 1 + target-arm/helper.c | 12 ++++++++++++ target-arm/translate.c | 10 ++++++++-- 5 files changed, 23 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index afdee9d..2b6b370 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -116,6 +116,7 @@ typedef struct ARMCPU { uint32_t reset_fpsid; uint32_t mvfr0; uint32_t mvfr1; + uint32_t mvfr2; uint32_t ctr; uint32_t reset_sctlr; uint32_t id_pfr0; diff --git a/target-arm/cpu.c b/target-arm/cpu.c index a3c7492..a78a36b 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -88,6 +88,7 @@ static void arm_cpu_reset(CPUState *s) env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; + env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; if (arm_feature(env, ARM_FEATURE_IWMMXT)) { env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 0ce4c26..ec0306b 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -572,6 +572,7 @@ enum arm_cpu_mode { /* VFP system registers. */ #define ARM_VFP_FPSID 0 #define ARM_VFP_FPSCR 1 +#define ARM_VFP_MVFR2 5 #define ARM_VFP_MVFR1 6 #define ARM_VFP_MVFR0 7 #define ARM_VFP_FPEXC 8 diff --git a/target-arm/helper.c b/target-arm/helper.c index e9b64f3..cf5fab8 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2155,6 +2155,18 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->id_aa64mmfr1 }, + { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, + .access = PL1_R, .type = ARM_CP_CONST, + .resetvalue = cpu->mvfr0 }, + { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, + .access = PL1_R, .type = ARM_CP_CONST, + .resetvalue = cpu->mvfr1 }, + { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, + .access = PL1_R, .type = ARM_CP_CONST, + .resetvalue = cpu->mvfr2 }, REGINFO_SENTINEL }; define_arm_cp_regs(cpu, v8_idregs); diff --git a/target-arm/translate.c b/target-arm/translate.c index 5d0c73f..6ea2352 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2963,9 +2963,10 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn) if ((insn & 0x0fe00fff) != 0x0ee00a10) return 1; rn = (insn >> 16) & 0xf; - if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC - && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0) + if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC && rn != ARM_VFP_MVFR2 + && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0) { return 1; + } } if (extract32(insn, 28, 4) == 0xf) { @@ -3111,6 +3112,11 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn) gen_helper_vfp_get_fpscr(tmp, cpu_env); } break; + case ARM_VFP_MVFR2: + if (!arm_feature(env, ARM_FEATURE_V8)) { + return 1; + } + /* fall through */ case ARM_VFP_MVFR0: case ARM_VFP_MVFR1: if (IS_USER(s)