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X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 45/51] allwinner-emac: update irq status after writes to interrupt registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Beniamino Galvani The irq line status must be updated after writes to the INT_CTL and INT_STA registers. Signed-off-by: Beniamino Galvani Reviewed-by: Peter Crosthwaite Message-id: 1395771730-16882-8-git-send-email-b.galvani@gmail.com Signed-off-by: Peter Maydell --- hw/net/allwinner_emac.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c index 91931ac..d780ba0 100644 --- a/hw/net/allwinner_emac.c +++ b/hw/net/allwinner_emac.c @@ -391,9 +391,11 @@ static void aw_emac_write(void *opaque, hwaddr offset, uint64_t value, break; case EMAC_INT_CTL_REG: s->int_ctl = value; + aw_emac_update_irq(s); break; case EMAC_INT_STA_REG: s->int_sta &= ~value; + aw_emac_update_irq(s); break; case EMAC_MAC_MADR_REG: s->phy_target = value;