From patchwork Fri May 2 13:45:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 29550 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ve0-f197.google.com (mail-ve0-f197.google.com [209.85.128.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id EBF5A203F3 for ; Fri, 2 May 2014 13:45:19 +0000 (UTC) Received: by mail-ve0-f197.google.com with SMTP id db11sf2393811veb.8 for ; Fri, 02 May 2014 06:45:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=2Qqsn5mgixh5kpaiOoSlVUoQ1G5qNC1pzWr0q657HmM=; b=hXM3cFvLfaqDCQo5HomCNjVNiA8GPepVpz2A7y7daYGCimuV48WwoXGvoMOLtsVFmN US+MnCfw+6rMj0ypmDoBo1nNcXHQIAKFmfMvxqE7zBAkufByy9BxZLZ3fLW4NC7AGy2/ EIBnT94I3gfHseWsU3MubKcqVv/6dv4b1WYOQfUm0e5ymRKf1cly+t2ewuUsXVaceZ/d 18gZ4BlCx1BojcoOmdyF4h1SJ3gNSL+67Vz5fjkseE9DKUHP/VwXmVsENcI0QypsSvXp 6vnNXsuhMY4jUIb7xyVg7zHHXYlsBwnCmS8YwQcfooNP724+2Xa8JR4Ssx8JHwzFoCEq uxXw== X-Gm-Message-State: ALoCoQnz9uQPwvFJB8NPZa+jDKusbPmfRSOIOoFkfeLLcMTmWJSeIULKI42zRnzT11Apu2rIhM1D X-Received: by 10.58.82.193 with SMTP id k1mr4572175vey.41.1399038319678; Fri, 02 May 2014 06:45:19 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.38.72 with SMTP id s66ls1508526qgs.85.gmail; Fri, 02 May 2014 06:45:19 -0700 (PDT) X-Received: by 10.52.15.226 with SMTP id a2mr158216vdd.69.1399038319560; Fri, 02 May 2014 06:45:19 -0700 (PDT) Received: from mail-ve0-f172.google.com (mail-ve0-f172.google.com [209.85.128.172]) by mx.google.com with ESMTPS id tm8si6704293vdc.44.2014.05.02.06.45.19 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 02 May 2014 06:45:19 -0700 (PDT) Received-SPF: none (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) client-ip=209.85.128.172; Received: by mail-ve0-f172.google.com with SMTP id jy13so5455267veb.3 for ; Fri, 02 May 2014 06:45:19 -0700 (PDT) X-Received: by 10.220.191.134 with SMTP id dm6mr13767181vcb.16.1399038319491; Fri, 02 May 2014 06:45:19 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp104051vcb; Fri, 2 May 2014 06:45:19 -0700 (PDT) X-Received: by 10.50.118.69 with SMTP id kk5mr4230209igb.10.1399038318182; Fri, 02 May 2014 06:45:18 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id k4si2742516igx.11.2014.05.02.06.45.17 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 02 May 2014 06:45:17 -0700 (PDT) Received-SPF: none (google.com: pm215@archaic.org.uk does not designate permitted sender hosts) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WgDm7-0002NL-Bs; Fri, 02 May 2014 14:45:15 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Riku Voipio Subject: [PATCH 2/4] linux-user/elfload.c: Update ARM HWCAP bits Date: Fri, 2 May 2014 14:45:13 +0100 Message-Id: <1399038315-9099-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1399038315-9099-1-git-send-email-peter.maydell@linaro.org> References: <1399038315-9099-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The kernel has added support for a number of new ARM HWCAP bits; add them to QEMU, including support for setting them where we have a corresponding CPU feature bit. We were also incorrectly setting the VFPv3D16 HWCAP -- this means "only 16 D registers", not "supports 16-bit floating point format"; since QEMU always has 32 D registers for VFPv3, we can just remove the line that incorrectly set this bit. The kernel does not set the HWCAP_FPA even if it is providing FPA emulation via nwfpe, so don't set this bit in QEMU either. Signed-off-by: Peter Maydell Cc: qemu-stable@nongnu.org --- linux-user/elfload.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 6cfaa3a..0449b29 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -351,6 +351,13 @@ enum ARM_HWCAP_ARM_NEON = 1 << 12, ARM_HWCAP_ARM_VFPv3 = 1 << 13, ARM_HWCAP_ARM_VFPv3D16 = 1 << 14, + ARM_HWCAP_ARM_TLS = 1 << 15, + ARM_HWCAP_ARM_VFPv4 = 1 << 16, + ARM_HWCAP_ARM_IDIVA = 1 << 17, + ARM_HWCAP_ARM_IDIVT = 1 << 18, + ARM_HWCAP_ARM_VFPD32 = 1 << 19, + ARM_HWCAP_ARM_LPAE = 1 << 20, + ARM_HWCAP_ARM_EVTSTRM = 1 << 21, }; #ifndef TARGET_AARCH64 @@ -428,17 +435,28 @@ static uint32_t get_elf_hwcap(void) hwcaps |= ARM_HWCAP_ARM_HALF; hwcaps |= ARM_HWCAP_ARM_THUMB; hwcaps |= ARM_HWCAP_ARM_FAST_MULT; - hwcaps |= ARM_HWCAP_ARM_FPA; /* probe for the extra features */ #define GET_FEATURE(feat, hwcap) \ do { if (arm_feature(&cpu->env, feat)) { hwcaps |= hwcap; } } while (0) + /* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */ + GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP); GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); - GET_FEATURE(ARM_FEATURE_VFP_FP16, ARM_HWCAP_ARM_VFPv3D16); + GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); + GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4); + GET_FEATURE(ARM_FEATURE_ARM_DIV, ARM_HWCAP_ARM_IDIVA); + GET_FEATURE(ARM_FEATURE_THUMB_DIV, ARM_HWCAP_ARM_IDIVT); + /* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.c. + * Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of + * ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated + * to our VFP_FP16 feature bit. + */ + GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPD32); + GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE); #undef GET_FEATURE return hwcaps;