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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id k6si21069419oeo.48.2014.06.07.13.11.22 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sat, 07 Jun 2014 13:11:23 -0700 (PDT) Received-SPF: none (google.com: pm215@archaic.org.uk does not designate permitted sender hosts) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WtMxV-0003jr-5s; Sat, 07 Jun 2014 21:11:21 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 1/3] target-arm: Add ULL suffix to calculation of page size Date: Sat, 7 Jun 2014 21:11:19 +0100 Message-Id: <1402171881-14343-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1402171881-14343-1-git-send-email-peter.maydell@linaro.org> References: <1402171881-14343-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.174 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The maximum block size for AArch64 address translation is 2GB. This means that we need a ULL suffix on our shift to avoid shifting into the sign bit of a signed 32 bit integer. Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite --- target-arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index ec031f5..cbad223 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3926,7 +3926,7 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, * These are basically the same thing, although the number * of bits we pull in from the vaddr varies. */ - page_size = (1 << ((granule_sz * (4 - level)) + 3)); + page_size = (1ULL << ((granule_sz * (4 - level)) + 3)); descaddr |= (address & (page_size - 1)); /* Extract attributes from the descriptor and merge with table attrs */ if (arm_feature(env, ARM_FEATURE_V8)) {