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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id f89si4417452qgf.112.2014.07.30.08.24.46 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 30 Jul 2014 08:24:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:51595 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XCVkE-0007t8-C1 for patch@linaro.org; Wed, 30 Jul 2014 11:24:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33761) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XCVgK-0001oe-MT for qemu-devel@nongnu.org; Wed, 30 Jul 2014 11:20:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XCVgE-00017x-9C for qemu-devel@nongnu.org; Wed, 30 Jul 2014 11:20:44 -0400 Received: from static.88-198-71-155.clients.your-server.de ([88.198.71.155]:44797 helo=socrates.bennee.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XCVgD-00017M-NY for qemu-devel@nongnu.org; Wed, 30 Jul 2014 11:20:38 -0400 Received: from localhost ([127.0.0.1] helo=zen.linaro.local) by socrates.bennee.com with esmtp (Exim 4.80) (envelope-from ) id 1XCVpr-0002Zs-3f; Wed, 30 Jul 2014 17:30:35 +0200 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Wed, 30 Jul 2014 16:20:27 +0100 Message-Id: <1406733627-24255-6-git-send-email-alex.bennee@linaro.org> X-Mailer: git-send-email 2.0.3 In-Reply-To: <1406733627-24255-1-git-send-email-alex.bennee@linaro.org> References: <1406733627-24255-1-git-send-email-alex.bennee@linaro.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 127.0.0.1 X-SA-Exim-Mail-From: alex.bennee@linaro.org X-SA-Exim-Scanned: No (on socrates.bennee.com); SAEximRunCond expanded to false X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 88.198.71.155 Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [Qemu-devel] [PATCH v2 5/5] target-arm: A64: disable a bunch of ARMv5 machines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: alex.bennee@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.176 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 If you attempt to run a system image which uses 1k pages in the qemu-system-aarch64 build it will fail thanks to the change to 12 bit pages. The boards are still available for the qemu-system-arm build. Signed-off-by: Alex Bennée diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-softmmu.mak index 6d3b5c7..2bf26a0 100644 --- a/default-configs/aarch64-softmmu.mak +++ b/default-configs/aarch64-softmmu.mak @@ -1,6 +1,9 @@ # Default configuration for aarch64-softmmu -# We support all the 32 bit boards so need all their config +# We support most of the 32 bit boards so need all their config include arm-softmmu.mak +# we explicitly disable ones that require old ARMv5 support +CONFIG_ARMV5_BOARDS=n + # Currently no 64-bit specific config requirements diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index f10cc69..1e5656e 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -63,6 +63,7 @@ CONFIG_BITBANG_I2C=y CONFIG_FRAMEBUFFER=y CONFIG_XILINX_SPIPS=y +CONFIG_ARMV5_BOARDS=y CONFIG_ARM11SCU=y CONFIG_A9SCU=y CONFIG_DIGIC=y diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 5899ed6..3dd87c6 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -1,8 +1,19 @@ -obj-y += boot.o collie.o exynos4_boards.o gumstix.o highbank.o +obj-y += boot.o collie.o exynos4_boards.o +obj-$(CONFIG_ARMV5_BOARDS) += gumstix.o +obj-y += highbank.o obj-$(CONFIG_DIGIC) += digic_boards.o -obj-y += integratorcp.o kzm.o mainstone.o musicpal.o nseries.o -obj-y += omap_sx1.o palm.o ranchu.o realview.o spitz.o stellaris.o -obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o +obj-$(CONFIG_ARMV5_BOARDS) += integratorcp.o +obj-y += kzm.o +obj-$(CONFIG_ARMV5_BOARDS) += mainstone.o +obj-$(CONFIG_ARMV5_BOARDS) += musicpal.o +obj-y += nseries.o +obj-y += omap_sx1.o palm.o ranchu.o realview.o +obj-$(CONFIG_ARMV5_BOARDS) += spitz.o +obj-y += stellaris.o +obj-$(CONFIG_ARMV5_BOARDS) += tosa.o +obj-$(CONFIG_ARMV5_BOARDS) +=versatilepb.o +obj-y += vexpress.o virt.o xilinx_zynq.o +obj-$(CONFIG_ARMV5_BOARDS) +=z2.o obj-y += lionhead.o obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 7e04e50..6152927 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -351,6 +351,7 @@ static void realview_init(QEMUMachineInitArgs *args, arm_load_kernel(ARM_CPU(first_cpu), &realview_binfo); } +#ifndef TARGET_AARCH64 static void realview_eb_init(QEMUMachineInitArgs *args) { if (!args->cpu_model) { @@ -358,6 +359,7 @@ static void realview_eb_init(QEMUMachineInitArgs *args) } realview_init(args, BOARD_EB); } +#endif static void realview_eb_mpcore_init(QEMUMachineInitArgs *args) { @@ -383,12 +385,14 @@ static void realview_pbx_a9_init(QEMUMachineInitArgs *args) realview_init(args, BOARD_PBX_A9); } +#ifndef TARGET_AARCH64 static QEMUMachine realview_eb_machine = { .name = "realview-eb", .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)", .init = realview_eb_init, .block_default_type = IF_SCSI, }; +#endif static QEMUMachine realview_eb_mpcore_machine = { .name = "realview-eb-mpcore", @@ -414,7 +418,9 @@ static QEMUMachine realview_pbx_a9_machine = { static void realview_machine_init(void) { +#ifndef TARGET_AARCH64 qemu_register_machine(&realview_eb_machine); +#endif qemu_register_machine(&realview_eb_mpcore_machine); qemu_register_machine(&realview_pb_a8_machine); qemu_register_machine(&realview_pbx_a9_machine); diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 6c6f2b3..3c0ad9a 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -398,6 +398,7 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) +#ifndef TARGET_AARCH64 static void arm926_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -452,6 +453,7 @@ static void arm1026_initfn(Object *obj) define_one_arm_cp_reg(cpu, &ifar); } } +#endif /* TARGET_AARCH64 */ static void arm1136_r2_initfn(Object *obj) { @@ -780,6 +782,7 @@ static void cortex_a15_initfn(Object *obj) define_arm_cp_regs(cpu, cortexa15_cp_reginfo); } +#ifndef TARGET_AARCH64 static void ti925t_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -947,6 +950,7 @@ static void pxa270c5_initfn(Object *obj) cpu->ctr = 0xd172172; cpu->reset_sctlr = 0x00000078; } +#endif /* TARGET_AARCH64 */ #ifdef CONFIG_USER_ONLY static void arm_any_initfn(Object *obj) @@ -975,24 +979,16 @@ typedef struct ARMCPUInfo { void (*class_init)(ObjectClass *oc, void *data); } ARMCPUInfo; +/* ARMv5 CPU models are disabled for the TARGET_AARCH64 build as they + * could potentially use the smaller 1k pages which we don't support + * for aarch64 + */ static const ARMCPUInfo arm_cpus[] = { #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) +#ifndef TARGET_AARCH64 { .name = "arm926", .initfn = arm926_initfn }, { .name = "arm946", .initfn = arm946_initfn }, { .name = "arm1026", .initfn = arm1026_initfn }, - /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an - * older core than plain "arm1136". In particular this does not - * have the v6K features. - */ - { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, - { .name = "arm1136", .initfn = arm1136_initfn }, - { .name = "arm1176", .initfn = arm1176_initfn }, - { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, - { .name = "cortex-m3", .initfn = cortex_m3_initfn, - .class_init = arm_v7m_class_init }, - { .name = "cortex-a8", .initfn = cortex_a8_initfn }, - { .name = "cortex-a9", .initfn = cortex_a9_initfn }, - { .name = "cortex-a15", .initfn = cortex_a15_initfn }, { .name = "ti925t", .initfn = ti925t_initfn }, { .name = "sa1100", .initfn = sa1100_initfn }, { .name = "sa1110", .initfn = sa1110_initfn }, @@ -1009,6 +1005,20 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, +#endif + /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an + * older core than plain "arm1136". In particular this does not + * have the v6K features. + */ + { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, + { .name = "arm1136", .initfn = arm1136_initfn }, + { .name = "arm1176", .initfn = arm1176_initfn }, + { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, + { .name = "cortex-m3", .initfn = cortex_m3_initfn, + .class_init = arm_v7m_class_init }, + { .name = "cortex-a8", .initfn = cortex_a8_initfn }, + { .name = "cortex-a9", .initfn = cortex_a9_initfn }, + { .name = "cortex-a15", .initfn = cortex_a15_initfn }, #ifdef CONFIG_USER_ONLY { .name = "any", .initfn = arm_any_initfn }, #endif