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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id f13si28654556qaa.110.2014.08.04.07.02.03 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 04 Aug 2014 07:02:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:52511 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XEIpv-0002kg-Gg for patch@linaro.org; Mon, 04 Aug 2014 10:02:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45356) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XEIiE-00059q-Fk for qemu-devel@nongnu.org; Mon, 04 Aug 2014 09:54:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XEIi9-0007Yf-93 for qemu-devel@nongnu.org; Mon, 04 Aug 2014 09:54:06 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:48908) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XEIi8-0006mN-VP for qemu-devel@nongnu.org; Mon, 04 Aug 2014 09:54:01 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XEIhd-0001Ay-75 for qemu-devel@nongnu.org; Mon, 04 Aug 2014 14:53:29 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 4 Aug 2014 14:53:23 +0100 Message-Id: <1407160408-4467-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1407160408-4467-1-git-send-email-peter.maydell@linaro.org> References: <1407160408-4467-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 07/12] target-arm: Make far_el1 an array X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.179 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: "Edgar E. Iglesias" No functional change. Prepares for future additions of the EL2 and 3 versions of this reg. Reviewed-by: Greg Bellows Signed-off-by: Edgar E. Iglesias Reviewed-by: Alex Bennée Message-id: 1402994746-8328-5-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- target-arm/cpu.c | 2 +- target-arm/cpu.h | 2 +- target-arm/helper-a64.c | 4 ++-- target-arm/helper.c | 12 ++++++------ 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 05e52e0..7cebb76 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -447,7 +447,7 @@ static void arm1026_initfn(Object *obj) ARMCPRegInfo ifar = { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, - .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el1), + .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]), .resetvalue = 0 }; define_one_arm_cp_reg(cpu, &ifar); diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 369d472..b755f99 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -187,7 +187,7 @@ typedef struct CPUARMState { uint32_t ifsr_el2; /* Fault status registers. */ uint64_t esr_el[2]; uint32_t c6_region[8]; /* MPU base/size registers. */ - uint64_t far_el1; /* Fault address registers. */ + uint64_t far_el[2]; /* Fault address registers. */ uint64_t par_el1; /* Translation result. */ uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 027434a..2e9ef64 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -465,13 +465,13 @@ void aarch64_cpu_do_interrupt(CPUState *cs) } env->cp15.esr_el[1] = env->exception.syndrome; - env->cp15.far_el1 = env->exception.vaddress; + env->cp15.far_el[1] = env->exception.vaddress; switch (cs->exception_index) { case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", - env->cp15.far_el1); + env->cp15.far_el[1]); break; case EXCP_BKPT: case EXCP_UDEF: diff --git a/target-arm/helper.c b/target-arm/helper.c index d343856..b5f2e57 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -521,7 +521,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { .access = PL0_W, .type = ARM_CP_NOP }, { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, .access = PL1_RW, - .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el1), + .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]), .resetvalue = 0, }, /* Watchpoint Fault Address Register : should actually only be present * for 1136, 1176, 11MPCore. @@ -1516,7 +1516,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { /* 64-bit FAR; this entry also gives us the AArch32 DFAR */ { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el1), + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), .resetvalue = 0, }, REGINFO_SENTINEL }; @@ -3425,8 +3425,8 @@ void arm_cpu_do_interrupt(CPUState *cs) /* Fall through to prefetch abort. */ case EXCP_PREFETCH_ABORT: env->cp15.ifsr_el2 = env->exception.fsr; - env->cp15.far_el1 = deposit64(env->cp15.far_el1, 32, 32, - env->exception.vaddress); + env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 32, 32, + env->exception.vaddress); qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", env->cp15.ifsr_el2, (uint32_t)env->exception.vaddress); new_mode = ARM_CPU_MODE_ABT; @@ -3436,8 +3436,8 @@ void arm_cpu_do_interrupt(CPUState *cs) break; case EXCP_DATA_ABORT: env->cp15.esr_el[1] = env->exception.fsr; - env->cp15.far_el1 = deposit64(env->cp15.far_el1, 0, 32, - env->exception.vaddress); + env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32, + env->exception.vaddress); qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", (uint32_t)env->cp15.esr_el[1], (uint32_t)env->exception.vaddress);