From patchwork Mon Aug 18 09:48:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 41369 Delivered-To: patches@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp138300vcb; Mon, 18 Aug 2014 02:49:52 -0700 (PDT) X-Received: by 10.194.89.36 with SMTP id bl4mr1263894wjb.126.1408355392270; Mon, 18 Aug 2014 02:49:52 -0700 (PDT) Return-Path: Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id md2si24466837wjb.172.2014.08.18.02.49.51 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 18 Aug 2014 02:49:52 -0700 (PDT) Received-SPF: none (google.com: pm215@archaic.org.uk does not designate permitted sender hosts) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=neutral (google.com: pm215@archaic.org.uk does not designate permitted sender hosts) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XJJYO-0000DP-5c; Mon, 18 Aug 2014 10:48:40 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Akos Kiss , David Long Subject: [PATCH] target-arm: Fix return address for A64 BRK instructions Date: Mon, 18 Aug 2014 10:48:40 +0100 Message-Id: <1408355320-802-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 When we take an exception resulting from a BRK instruction, the architecture requires that the "preferred return address" reported to the exception handler is the address of the BRK itself, not the following instruction (like undefined insns, and in contrast with SVC, HVC and SMC). Follow this, rather than incorrectly reporting the address of the following insn. (We do get this correct for the A32/T32 BKPT insns.) Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 33b5025..fc319d5 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1454,7 +1454,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) break; } /* BRK */ - gen_exception_insn(s, 0, EXCP_BKPT, syn_aa64_bkpt(imm16)); + gen_exception_insn(s, 4, EXCP_BKPT, syn_aa64_bkpt(imm16)); break; case 2: if (op2_ll != 0) {