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[81.2.115.146]) by mx.google.com with ESMTPS id 9si9418879lbr.25.2014.08.29.04.23.42 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 29 Aug 2014 04:23:43 -0700 (PDT) Received-SPF: none (google.com: pm215@archaic.org.uk does not designate permitted sender hosts) client-ip=81.2.115.146; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XNKFI-0004vF-IG; Fri, 29 Aug 2014 12:21:32 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paolo Bonzini , Richard Henderson Subject: [PATCH 09/10] target-arm: Remove comment about MDSCR_EL1 being dummy implementation Date: Fri, 29 Aug 2014 12:21:31 +0100 Message-Id: <1409311292-18860-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1409311292-18860-1-git-send-email-peter.maydell@linaro.org> References: <1409311292-18860-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , MDSCR_EL1 has actual functionality now; remove the out of date comment that claims it is a dummy implementation. Signed-off-by: Peter Maydell --- target-arm/helper.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index ef1eac9..6ae3c50 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2188,9 +2188,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, - /* Dummy implementation of monitor debug system control register: - * we don't support debug. (The 32-bit alias is DBGDSCRext.) - */ + /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, .access = PL1_RW,