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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id w33si5614866qge.86.2014.09.12.06.33.46 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 12 Sep 2014 06:33:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:44998 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XSQyw-0007SN-Cm for patch@linaro.org; Fri, 12 Sep 2014 09:33:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57018) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XSQpb-0006q9-NQ for qemu-devel@nongnu.org; Fri, 12 Sep 2014 09:24:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XSQpT-00040O-7w for qemu-devel@nongnu.org; Fri, 12 Sep 2014 09:24:07 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:46960) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XSQpT-0003xI-0w for qemu-devel@nongnu.org; Fri, 12 Sep 2014 09:23:59 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XSQpO-0003X4-Fv for qemu-devel@nongnu.org; Fri, 12 Sep 2014 14:23:54 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 12 Sep 2014 14:23:33 +0100 Message-Id: <1410528234-13545-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1410528234-13545-1-git-send-email-peter.maydell@linaro.org> References: <1410528234-13545-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 81.2.115.146 Subject: [Qemu-devel] [PULL 02/23] cpu-exec.c: Allow disabling of IRQs on ARM Cortex-M CPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.51 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: David Hoover Correct an error in the logic for deciding whether we can take an IRQ interrupt which meant that on M profile cores it was never possible to disable them. The design here is still bogus in that M profile doesn't have separate "IRQ" and "FIQ", which are an A/R profile concept; we should ideally implement the proper priority based scheme. Signed-off-by: David Hoover [PMM: Wrote a proper commit message] Signed-off-by: Peter Maydell --- cpu-exec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 7b5d2e2..e9adf56 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -618,8 +618,8 @@ int cpu_exec(CPUArchState *env) We avoid this by disabling interrupts when pc contains a magic address. */ if (interrupt_request & CPU_INTERRUPT_HARD - && ((IS_M(env) && env->regs[15] < 0xfffffff0) - || !(env->daif & PSTATE_I))) { + && !(env->daif & PSTATE_I) + && (!IS_M(env) || env->regs[15] < 0xfffffff0)) { cpu->exception_index = EXCP_IRQ; cc->do_interrupt(cpu); next_tb = 0;