From patchwork Mon Sep 29 18:26:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 38098 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wg0-f69.google.com (mail-wg0-f69.google.com [74.125.82.69]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id CF411201F1 for ; Mon, 29 Sep 2014 18:32:38 +0000 (UTC) Received: by mail-wg0-f69.google.com with SMTP id a1sf601605wgh.4 for ; Mon, 29 Sep 2014 11:32:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=/QhoOw6T+MkGx2LjxFs4IKUew0iOOIEYyx/tk8gfy0E=; b=ZcNfx3L3SFFQPdXCg5lY3XrjHYfq8IuactaBHQ/VQXSRNcHE67iFLuoW1bewYbloTK s5OS/oM8Z43prJzq2at0QyyH5yQDOpZf846EFx1SwdXA7wKRqkCx128x4SU1K5pzV4fh gnT7sECty2CLxfTLR6PGUCyb6Wme2cImzQ38gOOEpw9ouoOIyMqvwBl3XJYRVtZUhPUm YyQN43kDijoFKlmLtL4nVkqguwXrNqEFgXLJ10PCQHbmP5t738tmCCF/6D3gBN2z8+8n xEyzcmE4q4wApVcqJ9SEsFEZz47CEUTwG0inVcBuyj1vUlN2M+Lg3oBUWMY/rAOMEgry kZKg== X-Gm-Message-State: ALoCoQmrrAIV+HM+oLwua5sj/G9vOOV5DWC4OlFH/gXyvErNcAoTbyXda3NTrYOjuTEMtCN2zvs5 X-Received: by 10.180.38.11 with SMTP id c11mr512706wik.5.1412015557843; Mon, 29 Sep 2014 11:32:37 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.37.1 with SMTP id u1ls710698laj.20.gmail; Mon, 29 Sep 2014 11:32:37 -0700 (PDT) X-Received: by 10.112.134.229 with SMTP id pn5mr13275579lbb.22.1412015557684; Mon, 29 Sep 2014 11:32:37 -0700 (PDT) Received: from mail-la0-f44.google.com (mail-la0-f44.google.com [209.85.215.44]) by mx.google.com with ESMTPS id e10si19371553lae.93.2014.09.29.11.32.37 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 29 Sep 2014 11:32:37 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) client-ip=209.85.215.44; Received: by mail-la0-f44.google.com with SMTP id gi9so8343958lab.31 for ; Mon, 29 Sep 2014 11:32:37 -0700 (PDT) X-Received: by 10.112.4.33 with SMTP id h1mr38415310lbh.67.1412015557561; Mon, 29 Sep 2014 11:32:37 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.130.169 with SMTP id of9csp225146lbb; Mon, 29 Sep 2014 11:32:36 -0700 (PDT) X-Received: by 10.140.83.209 with SMTP id j75mr5793963qgd.91.1412015555234; Mon, 29 Sep 2014 11:32:35 -0700 (PDT) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id g9si14409061qgf.49.2014.09.29.11.32.34 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 29 Sep 2014 11:32:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:38351 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XYfkQ-0008HT-3e for patch@linaro.org; Mon, 29 Sep 2014 14:32:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40877) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XYff9-0008Co-PV for qemu-devel@nongnu.org; Mon, 29 Sep 2014 14:27:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XYff8-0007V6-Di for qemu-devel@nongnu.org; Mon, 29 Sep 2014 14:27:07 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:54082) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XYff8-0007L2-6A for qemu-devel@nongnu.org; Mon, 29 Sep 2014 14:27:06 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XYfew-0005p9-P0 for qemu-devel@nongnu.org; Mon, 29 Sep 2014 19:26:54 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 29 Sep 2014 19:26:53 +0100 Message-Id: <1412015213-22268-20-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1412015213-22268-1-git-send-email-peter.maydell@linaro.org> References: <1412015213-22268-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 19/19] target-arm: Add support for VIRQ and VFIQ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: "Edgar E. Iglesias" This only implements the external delivery method via the GIC. Acked-by: Greg Bellows Signed-off-by: Edgar E. Iglesias Message-id: 1411718914-6608-12-git-send-email-edgar.iglesias@gmail.com [PMM: adjusted following cpu-exec refactoring] Signed-off-by: Peter Maydell --- target-arm/cpu.c | 47 ++++++++++++++++++++++++++++++++++++----------- target-arm/cpu.h | 35 ++++++++++++++++++++++++++++++++--- target-arm/helper-a64.c | 2 ++ target-arm/helper.c | 4 ++++ target-arm/internals.h | 2 ++ 5 files changed, 76 insertions(+), 14 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index b7cdcd7..8ab6d95 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -41,7 +41,9 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) static bool arm_cpu_has_work(CPUState *cs) { return cs->interrupt_request & - (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); + (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD + | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ + | CPU_INTERRUPT_EXITTB); } static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) @@ -210,6 +212,18 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) cc->do_interrupt(cs); ret = true; } + if (interrupt_request & CPU_INTERRUPT_VIRQ + && arm_excp_unmasked(cs, EXCP_VIRQ)) { + cs->exception_index = EXCP_VIRQ; + cc->do_interrupt(cs); + ret = true; + } + if (interrupt_request & CPU_INTERRUPT_VFIQ + && arm_excp_unmasked(cs, EXCP_VFIQ)) { + cs->exception_index = EXCP_VFIQ; + cc->do_interrupt(cs); + ret = true; + } return ret; } @@ -218,21 +232,29 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) static void arm_cpu_set_irq(void *opaque, int irq, int level) { ARMCPU *cpu = opaque; + CPUARMState *env = &cpu->env; CPUState *cs = CPU(cpu); + static const int mask[] = { + [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, + [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, + [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, + [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ + }; switch (irq) { - case ARM_CPU_IRQ: - if (level) { - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + case ARM_CPU_VIRQ: + case ARM_CPU_VFIQ: + if (!arm_feature(env, ARM_FEATURE_EL2)) { + hw_error("%s: Virtual interrupt line %d with no EL2 support\n", + __func__, irq); } - break; + /* fall through */ + case ARM_CPU_IRQ: case ARM_CPU_FIQ: if (level) { - cpu_interrupt(cs, CPU_INTERRUPT_FIQ); + cpu_interrupt(cs, mask[irq]); } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ); + cpu_reset_interrupt(cs, mask[irq]); } break; default: @@ -282,9 +304,12 @@ static void arm_cpu_initfn(Object *obj) #ifndef CONFIG_USER_ONLY /* Our inbound IRQ and FIQ lines */ if (kvm_enabled()) { - qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2); + /* VIRQ and VFIQ are unused with KVM but we add them to maintain + * the same interface as non-KVM CPUs. + */ + qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); } else { - qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2); + qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); } cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 11ba9d6..65a3417 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -54,6 +54,8 @@ #define EXCP_HVC 11 /* HyperVisor Call */ #define EXCP_HYP_TRAP 12 #define EXCP_SMC 13 /* Secure Monitor Call */ +#define EXCP_VIRQ 14 +#define EXCP_VFIQ 15 #define ARMV7M_EXCP_RESET 1 #define ARMV7M_EXCP_NMI 2 @@ -68,6 +70,8 @@ /* ARM-specific interrupt pending bits. */ #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 +#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 +#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 /* The usual mapping for an AArch64 system register to its AArch32 * counterpart is for the 32 bit world to have access to the lower @@ -83,9 +87,11 @@ #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) #endif -/* Meanings of the ARMCPU object's two inbound GPIO lines */ +/* Meanings of the ARMCPU object's four inbound GPIO lines */ #define ARM_CPU_IRQ 0 #define ARM_CPU_FIQ 1 +#define ARM_CPU_VIRQ 2 +#define ARM_CPU_VFIQ 3 typedef void ARMWriteCPFunc(void *opaque, int cp_info, int srcreg, int operand, uint32_t value); @@ -1184,6 +1190,18 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) bool secure = false; /* If in EL1/0, Physical IRQ routing to EL2 only happens from NS state. */ bool irq_can_hyp = !secure && cur_el < 2 && target_el == 2; + /* ARMv7-M interrupt return works by loading a magic value + * into the PC. On real hardware the load causes the + * return to occur. The qemu implementation performs the + * jump normally, then does the exception return when the + * CPU tries to execute code at the magic address. + * This will cause the magic PC value to be pushed to + * the stack if an interrupt occurred at the wrong time. + * We avoid this by disabling interrupts when + * pc contains a magic address. + */ + bool irq_unmasked = !(env->daif & PSTATE_I) + && (!IS_M(env) || env->regs[15] < 0xfffffff0); /* Don't take exceptions if they target a lower EL. */ if (cur_el > target_el) { @@ -1200,8 +1218,19 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_IMO)) { return true; } - return !(env->daif & PSTATE_I) - && (!IS_M(env) || env->regs[15] < 0xfffffff0); + return irq_unmasked; + case EXCP_VFIQ: + if (!secure && !(env->cp15.hcr_el2 & HCR_FMO)) { + /* VFIQs are only taken when hypervized and non-secure. */ + return false; + } + return !(env->daif & PSTATE_F); + case EXCP_VIRQ: + if (!secure && !(env->cp15.hcr_el2 & HCR_IMO)) { + /* VIRQs are only taken when hypervized and non-secure. */ + return false; + } + return irq_unmasked; default: g_assert_not_reached(); } diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 0011488..8228e29 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -482,9 +482,11 @@ void aarch64_cpu_do_interrupt(CPUState *cs) env->cp15.esr_el[new_el] = env->exception.syndrome; break; case EXCP_IRQ: + case EXCP_VIRQ: addr += 0x80; break; case EXCP_FIQ: + case EXCP_VFIQ: addr += 0x100; break; default: diff --git a/target-arm/helper.c b/target-arm/helper.c index 6135594..2669e15 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3804,6 +3804,10 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) } break; } + case EXCP_VIRQ: + case EXCP_VFIQ: + target_el = 1; + break; default: target_el = MAX(cur_el, 1); break; diff --git a/target-arm/internals.h b/target-arm/internals.h index 1486595..b7547bb 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -56,6 +56,8 @@ static const char * const excnames[] = { [EXCP_HVC] = "Hypervisor Call", [EXCP_HYP_TRAP] = "Hypervisor Trap", [EXCP_SMC] = "Secure Monitor Call", + [EXCP_VIRQ] = "Virtual IRQ", + [EXCP_VFIQ] = "Virtual FIQ", }; static inline void arm_log_exception(int idx)