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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id ej8si4584147lad.66.2014.10.09.07.30.29 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 09 Oct 2014 07:30:29 -0700 (PDT) Received-SPF: temperror (google.com: error in processing during lookup of pm215@archaic.org.uk: DNS timeout) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XcEjc-0004cP-6l; Thu, 09 Oct 2014 15:30:28 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Ard Biesheuvel , Greg Bellows Subject: [PATCH v5 1/7] target-arm: add powered off cpu state Date: Thu, 9 Oct 2014 15:30:22 +0100 Message-Id: <1412865028-17725-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1412865028-17725-1-git-send-email-peter.maydell@linaro.org> References: <1412865028-17725-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.178 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Rob Herring Add tracking of cpu power state in order to support powering off of cores in system emuluation. The initial state is determined by the start-powered-off QOM property. Signed-off-by: Rob Herring Reviewed-by: Peter Maydell Signed-off-by: Ard Biesheuvel Signed-off-by: Peter Maydell --- target-arm/cpu-qom.h | 2 ++ target-arm/cpu.c | 8 +++++++- target-arm/machine.c | 5 +++-- 3 files changed, 12 insertions(+), 3 deletions(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 96a3da9..aeb7e1d 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -98,6 +98,8 @@ typedef struct ARMCPU { /* Should CPU start in PSCI powered-off state? */ bool start_powered_off; + /* CPU currently in PSCI powered-off state */ + bool powered_off; /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. diff --git a/target-arm/cpu.c b/target-arm/cpu.c index edfd586..67cd176 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -40,7 +40,10 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) static bool arm_cpu_has_work(CPUState *cs) { - return cs->interrupt_request & + ARMCPU *cpu = ARM_CPU(cs); + + return !cpu->powered_off + && cs->interrupt_request & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_EXITTB); @@ -93,6 +96,9 @@ static void arm_cpu_reset(CPUState *s) env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; + cpu->powered_off = cpu->start_powered_off; + s->halted = cpu->start_powered_off; + if (arm_feature(env, ARM_FEATURE_IWMMXT)) { env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; } diff --git a/target-arm/machine.c b/target-arm/machine.c index ddb7d05..5776ee0 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -222,8 +222,8 @@ static int cpu_post_load(void *opaque, int version_id) const VMStateDescription vmstate_arm_cpu = { .name = "cpu", - .version_id = 20, - .minimum_version_id = 20, + .version_id = 21, + .minimum_version_id = 21, .pre_save = cpu_pre_save, .post_load = cpu_post_load, .fields = (VMStateField[]) { @@ -263,6 +263,7 @@ const VMStateDescription vmstate_arm_cpu = { VMSTATE_UINT64(env.exception.vaddress, ARMCPU), VMSTATE_TIMER(gt_timer[GTIMER_PHYS], ARMCPU), VMSTATE_TIMER(gt_timer[GTIMER_VIRT], ARMCPU), + VMSTATE_BOOL(powered_off, ARMCPU), VMSTATE_END_OF_LIST() }, .subsections = (VMStateSubsection[]) {