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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id t10si4469536wiw.59.2014.10.10.11.46.49 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 10 Oct 2014 11:46:49 -0700 (PDT) Received-SPF: none (google.com: pm215@archaic.org.uk does not designate permitted sender hosts) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XcfDD-0005Qf-7n; Fri, 10 Oct 2014 19:46:47 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Laurent Desnogues Subject: [PATCH] target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any" Date: Fri, 10 Oct 2014 19:46:47 +0100 Message-Id: <1412966807-20844-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , For the CPU type "any" (only used with linux-user) we were reporting the L1Ip field as 0b00, which is reserved. Change this field to 0b10 instead, indicating a VIPT icache as the comment describes. Signed-off-by: Peter Maydell Reviewed-by: Laurent Desnogues --- target-arm/cpu64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index c30f47e..4807ce1 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -151,7 +151,7 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); - cpu->ctr = 0x80030003; /* 32 byte I and D cacheline size, VIPT icache */ + cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ } #endif