From patchwork Fri Oct 10 18:57:27 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 38632 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ee0-f69.google.com (mail-ee0-f69.google.com [74.125.83.69]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id D99A9202DB for ; Fri, 10 Oct 2014 18:57:29 +0000 (UTC) Received: by mail-ee0-f69.google.com with SMTP id b15sf2550087eek.0 for ; Fri, 10 Oct 2014 11:57:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=g1GwTuuoc+mHVTI7Yg6rj/zuVkpZD/g+mT+WYQb3DNQ=; b=PMQy7Ucnd4p7HgIkJnODs+QeRf7PfKGqMQVJbf/KIMQxv5TOCLahvzf/yuoYRIOxqE mYFZjAMe69vjd34fzZT5mV/JCxIDHbE/o5rIr9141uKn9BN5k5YwHORQi/CXsyZkPPUP +mcPsL+/BwpTKwyIaCv08tkjEsGv/AI1WH+5ZyqSPH+WhyenqmKIfl88N2mXJ4RmnRNU GKj6qI1gAX6ofM+tzpqzRFhZ/jWY7Vd1G6EjG5ck9jOc94AIOq7lkscpFqB/zy940iJM N2j7MHjIMV5tOEsKZ1dVtBiYRRFOaX+SouJcgemwPSA7/Mn77gl0TalBxPrPYHhp0RWN /Ujw== X-Gm-Message-State: ALoCoQnpjAagXwJHCrD7UBQdPVNAbfXl3YnvWYRfwmtuBA4REpT9igFv9A9DbkunkkphMcPOyXVa X-Received: by 10.194.8.194 with SMTP id t2mr4179wja.7.1412967449044; Fri, 10 Oct 2014 11:57:29 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.21.135 with SMTP id v7ls315335lae.40.gmail; Fri, 10 Oct 2014 11:57:28 -0700 (PDT) X-Received: by 10.112.166.6 with SMTP id zc6mr6753234lbb.31.1412967448860; Fri, 10 Oct 2014 11:57:28 -0700 (PDT) Received: from mail-la0-f45.google.com (mail-la0-f45.google.com [209.85.215.45]) by mx.google.com with ESMTPS id d7si10742362laa.24.2014.10.10.11.57.28 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 10 Oct 2014 11:57:28 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.45 as permitted sender) client-ip=209.85.215.45; Received: by mail-la0-f45.google.com with SMTP id q1so3825012lam.4 for ; Fri, 10 Oct 2014 11:57:28 -0700 (PDT) X-Received: by 10.112.156.227 with SMTP id wh3mr6679961lbb.23.1412967448780; Fri, 10 Oct 2014 11:57:28 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.112.84.229 with SMTP id c5csp481611lbz; Fri, 10 Oct 2014 11:57:28 -0700 (PDT) X-Received: by 10.194.23.106 with SMTP id l10mr4758606wjf.123.1412967448221; Fri, 10 Oct 2014 11:57:28 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id ct5si9630013wjb.7.2014.10.10.11.57.28 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 10 Oct 2014 11:57:28 -0700 (PDT) Received-SPF: none (google.com: pm215@archaic.org.uk does not designate permitted sender hosts) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XcfNX-0005S4-8G; Fri, 10 Oct 2014 19:57:27 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Laurent Desnogues Subject: [PATCH] target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0 Date: Fri, 10 Oct 2014 19:57:27 +0100 Message-Id: <1412967447-20931-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.45 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The ARM ARM requires that the FPINST and FPINST2 VFP control registers are not accessible to code at EL0. We were already correctly implementing this for reads of these registers; add the missing check for the write code path. Signed-off-by: Peter Maydell Reviewed-by: Laurent Desnogues --- target-arm/translate.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target-arm/translate.c b/target-arm/translate.c index 8a2994f..d8ee2e4 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -3199,6 +3199,9 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn) break; case ARM_VFP_FPINST: case ARM_VFP_FPINST2: + if (IS_USER(s)) { + return 1; + } tmp = load_reg(s, rd); store_cpu_field(tmp, vfp.xregs[rn]); break;