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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id v10si8603441vcl.87.2014.10.21.10.09.27 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 21 Oct 2014 10:09:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:52500 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcw0-0002B2-9s for patch@linaro.org; Tue, 21 Oct 2014 13:09:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42118) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjF-0006oz-B1 for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xgcj9-0006t2-22 for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:13 -0400 Received: from mail-qa0-f45.google.com ([209.85.216.45]:45579) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcj8-0006sh-Tx for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:06 -0400 Received: by mail-qa0-f45.google.com with SMTP id cm18so1125570qab.18 for ; Tue, 21 Oct 2014 09:56:03 -0700 (PDT) X-Received: by 10.229.248.5 with SMTP id me5mr47751758qcb.2.1413910563093; Tue, 21 Oct 2014 09:56:03 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com ([67.52.129.61]) by mx.google.com with ESMTPSA id a3sm11122116qaa.49.2014.10.21.09.56.02 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 09:56:02 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 21 Oct 2014 11:55:24 -0500 Message-Id: <1413910544-20150-13-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> References: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.216.45 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v7 12/32] target-arm: add secure state bit to CPREG hash X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=temperror (google.com: error in processing during lookup of patch+caf_=patchwork-forward=linaro.org@linaro.org: DNS timeout) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Added additional NS-bit to CPREG hash encoding. Updated hash lookup locations to specify hash bit currently set to non-secure. Signed-off-by: Greg Bellows ========== v5 -> v6 - Globally replace Aarch# with AArch# Signed-off-by: Greg Bellows --- target-arm/cpu.h | 25 ++++++++++++++++++++----- target-arm/helper.c | 6 +++--- target-arm/translate.c | 16 ++++++++++------ 3 files changed, 33 insertions(+), 14 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 786deac..4273621 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -876,6 +876,7 @@ void armv7m_nvic_complete_irq(void *opaque, int irq); * Crn, Crm, opc1, opc2 fields * 32 or 64 bit register (ie is it accessed via MRC/MCR * or via MRRC/MCRR?) + * non-secure/secure bank (AArch32 only) * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. * (In this case crn and opc2 should be zero.) * For AArch64, there is no 32/64 bit size distinction; @@ -893,9 +894,16 @@ void armv7m_nvic_complete_irq(void *opaque, int irq); #define CP_REG_AA64_SHIFT 28 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) -#define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2) \ - (((cp) << 16) | ((is64) << 15) | ((crn) << 11) | \ - ((crm) << 7) | ((opc1) << 3) | (opc2)) +/* To enable banking of coprocessor registers depending on ns-bit we + * add a bit to distinguish between secure and non-secure cpregs in the + * hashtable. + */ +#define CP_REG_NS_SHIFT 29 +#define CP_REG_NS_MASK(nsbit) (nsbit << CP_REG_NS_SHIFT) + +#define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2, ns) \ + (CP_REG_NS_MASK(ns) | ((cp) << 16) | ((is64) << 15) | \ + ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ (CP_REG_AA64_MASK | \ @@ -914,8 +922,15 @@ static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) uint32_t cpregid = kvmid; if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { cpregid |= CP_REG_AA64_MASK; - } else if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { - cpregid |= (1 << 15); + } else { + if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { + cpregid |= (1 << 15); + } + + /* KVM is always non-secure so add the NS flag on AArch32 register + * entries. + */ + cpregid |= CP_REG_NS_MASK(SCR_NS); } return cpregid; } diff --git a/target-arm/helper.c b/target-arm/helper.c index 78aeb31..5f3bdc0 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3288,7 +3288,7 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, void *opaque, int state, - int crm, int opc1, int opc2) + int crm, int opc1, int opc2, int nsbit) { /* Private utility function for define_one_arm_cp_reg_with_opaque(): * add a single reginfo struct to the hash table. @@ -3327,7 +3327,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, r2->opc0, opc1, opc2); } else { - *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2); + *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2, nsbit); } if (opaque) { r2->opaque = opaque; @@ -3477,7 +3477,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, continue; } add_cpreg_to_hashtable(cpu, r, opaque, state, - crm, opc1, opc2); + crm, opc1, opc2, SCR_NS); } } } diff --git a/target-arm/translate.c b/target-arm/translate.c index aa17a20..459fedc 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -712,7 +712,7 @@ static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32 b) /* * generate a conditional branch based on ARM condition code cc. - * This is common between ARM and Aarch64 targets. + * This is common between ARM and AArch64 targets. */ void arm_gen_test_cc(int cc, int label) { @@ -7071,7 +7071,7 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn) rt = (insn >> 12) & 0xf; ri = get_arm_cp_reginfo(s->cp_regs, - ENCODE_CP_REG(cpnum, is64, crn, crm, opc1, opc2)); + ENCODE_CP_REG(cpnum, is64, crn, crm, opc1, opc2, s->ns)); if (ri) { /* Check access permissions */ if (!cp_access_ok(s->current_el, ri, isread)) { @@ -7261,12 +7261,16 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn) */ if (is64) { qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 " - "64 bit system register cp:%d opc1: %d crm:%d\n", - isread ? "read" : "write", cpnum, opc1, crm); + "64 bit system register cp:%d opc1: %d crm:%d " + "(%s)\n", + isread ? "read" : "write", cpnum, opc1, crm, + s->ns ? "non-secure" : "secure"); } else { qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 " - "system register cp:%d opc1:%d crn:%d crm:%d opc2:%d\n", - isread ? "read" : "write", cpnum, opc1, crn, crm, opc2); + "system register cp:%d opc1:%d crn:%d crm:%d opc2:%d " + "(%s)\n", + isread ? "read" : "write", cpnum, opc1, crn, crm, opc2, + s->ns ? "non-secure" : "secure"); } return 1;