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[208.118.235.17]) by mx.google.com with ESMTPS id y104si23404229qgd.126.2014.10.21.10.04.23 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 21 Oct 2014 10:04:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Received: from localhost ([::1]:52465 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcr8-0002V8-Ip for patch@linaro.org; Tue, 21 Oct 2014 13:04:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42120) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjF-0006p7-CO for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XgcjA-0006tt-1S for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:13 -0400 Received: from mail-qa0-f53.google.com ([209.85.216.53]:36867) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcj9-0006tU-Td for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:07 -0400 Received: by mail-qa0-f53.google.com with SMTP id v10so1121637qac.40 for ; Tue, 21 Oct 2014 09:56:07 -0700 (PDT) X-Received: by 10.224.88.136 with SMTP id a8mr47748692qam.63.1413910567297; Tue, 21 Oct 2014 09:56:07 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com ([67.52.129.61]) by mx.google.com with ESMTPSA id a3sm11122116qaa.49.2014.10.21.09.56.06 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 09:56:06 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 21 Oct 2014 11:55:29 -0500 Message-Id: <1413910544-20150-18-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> References: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.216.53 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v7 17/32] target-arm: add NSACR register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.176 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler Implements NSACR register with corresponding read/write functions for ARMv7 and ARMv8. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ---------- v4 -> v5 - Changed to use renamed arm_current_el() Signed-off-by: Greg Bellows --- target-arm/cpu.h | 6 +++++ target-arm/helper.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 73 insertions(+), 1 deletion(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 4273621..f9221a4 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -181,6 +181,7 @@ typedef struct CPUARMState { uint64_t c1_sys; /* System control register. */ uint64_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ + uint32_t c1_nsacr; /* Non-secure access control register. */ uint64_t ttbr0_el1; /* MMU translation table base 0. */ uint64_t ttbr1_el1; /* MMU translation table base 1. */ uint64_t c2_control; /* MMU translation table base control. */ @@ -634,6 +635,11 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) +#define NSACR_NSTRCDIS (1U << 20) +#define NSACR_RFR (1U << 19) +#define NSACR_NSASEDIS (1U << 15) +#define NSACR_NSD32DIS (1U << 14) + /* Return the current FPSCR value. */ uint32_t vfp_get_fpscr(CPUARMState *env); void vfp_set_fpscr(CPUARMState *env, uint32_t val); diff --git a/target-arm/helper.c b/target-arm/helper.c index 2af8fbb..f12181f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -520,7 +520,19 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, /* VFP coprocessor: cp10 & cp11 [23:20] */ mask |= (1 << 31) | (1 << 30) | (0xf << 20); - if (!arm_feature(env, ARM_FEATURE_NEON)) { + if (arm_feature(env, ARM_FEATURE_NEON)) { + /* NSACR can disable non-secure writes to + * ASEDIS [31] or D32DIS [30] + */ + if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env)) { + if ((env->cp15.c1_nsacr & NSACR_NSASEDIS)) { + mask &= ~(1 << 31); + } + if ((env->cp15.c1_nsacr & NSACR_NSD32DIS)) { + mask &= ~(1 << 30); + } + } + } else { /* ASEDIS [31] bit is RAO/WI */ value |= (1 << 31); } @@ -532,6 +544,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, !arm_feature(env, ARM_FEATURE_VFP3)) { /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ value |= (1 << 30); + mask |= (1 << 30); } } value &= mask; @@ -2310,6 +2323,55 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { REGINFO_SENTINEL }; +static void nsacr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint32_t mask = 0; + + /* Pre ARMv8 some bits are RAO or UNK/SBZP */ + if (!arm_feature(env, ARM_FEATURE_V8)) { + + if (arm_feature(env, ARM_FEATURE_VFP)) { + mask |= NSACR_NSASEDIS | NSACR_NSD32DIS; + + if (!arm_feature(env, ARM_FEATURE_NEON)) { + /* NSASEDIS are RAO/WI */ + value |= NSACR_NSASEDIS; + } + + /* VFPv3 and upwards with NEON implement 32 double precision + * registers (D0-D31). + */ + if (!arm_feature(env, ARM_FEATURE_NEON) || + !arm_feature(env, ARM_FEATURE_VFP3)) { + /* NSD32DIS is RAO/WI if D16-31 are not implemented. */ + value |= NSACR_NSD32DIS; + } + } + + /* cpn bits [13:0] */ + mask = 0x3fff; + + value &= mask; + } + + raw_write(env, ri, value); +} + +static uint64_t nsacr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t ret = raw_read(env, ri); + + if (arm_feature(env, ARM_FEATURE_V8)) { + if (!arm_feature(env, ARM_FEATURE_EL3) || ( + arm_el_is_aa64(env, 3) && !is_a64(env) && + arm_current_el(env) != 3)) { + ret = 0x0000C00; + } + } + return ret; +} + static const ARMCPRegInfo v8_el3_cp_reginfo[] = { { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, @@ -2347,6 +2409,10 @@ static const ARMCPRegInfo v7_el3_cp_reginfo[] = { { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), .resetvalue = 0, .writefn = scr_write}, + { .name = "NSACR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 2, + .access = PL3_RW | PL1_R, .resetvalue = 0, + .writefn = nsacr_write, .readfn = nsacr_read, + .fieldoffset = offsetof(CPUARMState, cp15.c1_nsacr) }, REGINFO_SENTINEL };