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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id h3si23480735qan.61.2014.10.21.10.05.15 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 21 Oct 2014 10:05:16 -0700 (PDT) Received-SPF: temperror (google.com: error in processing during lookup of qemu-devel-bounces+patch=linaro.org@nongnu.org: DNS timeout) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:52471 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcrz-0003xD-E4 for patch@linaro.org; Tue, 21 Oct 2014 13:05:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42039) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjA-0006jl-GW for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xgcj1-0006ox-WD for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:08 -0400 Received: from mail-qg0-f43.google.com ([209.85.192.43]:57946) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcj1-0006ol-R5 for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:55:59 -0400 Received: by mail-qg0-f43.google.com with SMTP id j107so1201158qga.30 for ; Tue, 21 Oct 2014 09:55:59 -0700 (PDT) X-Received: by 10.229.86.194 with SMTP id t2mr47507709qcl.20.1413910557480; Tue, 21 Oct 2014 09:55:57 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com ([67.52.129.61]) by mx.google.com with ESMTPSA id a3sm11122116qaa.49.2014.10.21.09.55.56 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 09:55:57 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 21 Oct 2014 11:55:18 -0500 Message-Id: <1413910544-20150-7-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> References: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.43 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v7 06/32] target-arm: A32: Emulate the SMC instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.50 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler Implements SMC instruction in AArch32 using the A32 syndrome. When executing SMC instruction from monitor CPU mode SCR.NS bit is reset. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell ========== v5 -> v6 - Fixed PC offsetting for presmc - Removed extraneous semi-colon - Fixed merge issue v4 -> v5 - Merge pre_smc upstream changes and incorporated ss_advance Signed-off-by: Greg Bellows --- target-arm/helper.c | 11 +++++++++++ target-arm/op_helper.c | 3 +-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 033b18f..38d9f7b 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -4091,6 +4091,12 @@ void arm_cpu_do_interrupt(CPUState *cs) mask = CPSR_A | CPSR_I | CPSR_F; offset = 4; break; + case EXCP_SMC: + new_mode = ARM_CPU_MODE_MON; + addr = 0x08; + mask = CPSR_A | CPSR_I | CPSR_F; + offset = 0; + break; default: cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); return; /* Never happens. Keep compiler happy. */ @@ -4109,6 +4115,11 @@ void arm_cpu_do_interrupt(CPUState *cs) */ addr += env->cp15.vbar_el[1]; } + + if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { + env->cp15.scr_el3 &= ~SCR_NS; + } + switch_mode (env, new_mode); /* For exceptions taken to AArch32 we must clear the SS bit in both * PSTATE and in the old-state value we save to SPSR_, so zero it now. diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 6cc3387..62012c3 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -429,8 +429,7 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) { ARMCPU *cpu = arm_env_get_cpu(env); int cur_el = arm_current_el(env); - /* FIXME: Use real secure state. */ - bool secure = false; + bool secure = arm_is_secure(env); bool smd = env->cp15.scr_el3 & SCR_SMD; /* On ARMv8 AArch32, SMD only applies to NS state. * On ARMv7 SMD only applies to NS state and only if EL2 is available.