From patchwork Tue Nov 4 12:30:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 40144 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f198.google.com (mail-wi0-f198.google.com [209.85.212.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id F1BAE240A6 for ; Tue, 4 Nov 2014 12:33:54 +0000 (UTC) Received: by mail-wi0-f198.google.com with SMTP id n3sf3931753wiv.5 for ; Tue, 04 Nov 2014 04:33:54 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:mime-version:subject:precedence:list-id:list-unsubscribe :list-archive:list-post:list-help:list-subscribe:errors-to:sender :x-original-sender:x-original-authentication-results:mailing-list :content-type:content-transfer-encoding; bh=3G9aUT8f+8Mfc0hQ8IiZN5z30/mDDwcoWkd9M5hMFww=; b=k068v2vs+LcZXwe6OZC+LXorfv2LiOE665cspKaaCvikuUba03GGcwZFyTNniMlwX4 D1e9XvHWLoizCBlF1//wySlQcUMxAl8CrogQgST2e1VR5r/6pB46sQw6lc5Oatd3rFFd WK6J/hTly0bv3uhRHmRuFqdyLH2HBrzSfo4k94n5x0KIqYhex2Z0t7iTZnaiDuux+wdy gZYUrp3XykqrqgdKTffOM9ucVRgbXXzK35aoSGL9Z3thukrHqtMB/VZ75+8MVE8XCqKE r0qq2Rkh+Po7CWmd9fp/F3WA9o2V+AGthL5bDEeXxiLdQ3rGWWdCK1Wy6Z+xX3KVWCou LcEg== X-Gm-Message-State: ALoCoQmwe7OwYUDQo4gEYldCsTmYZ+oBgsohz9tiK/B08C3rZbP8Daaw6Nf0jaRfbKlPHEQmVaTx X-Received: by 10.112.180.71 with SMTP id dm7mr354667lbc.18.1415104433949; Tue, 04 Nov 2014 04:33:53 -0800 (PST) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.5.5 with SMTP id o5ls227307lao.3.gmail; Tue, 04 Nov 2014 04:33:53 -0800 (PST) X-Received: by 10.112.168.39 with SMTP id zt7mr10566222lbb.72.1415104433810; Tue, 04 Nov 2014 04:33:53 -0800 (PST) Received: from mail-la0-f46.google.com (mail-la0-f46.google.com. [209.85.215.46]) by mx.google.com with ESMTPS id t13si375184lal.121.2014.11.04.04.33.53 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 04 Nov 2014 04:33:53 -0800 (PST) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.46 as permitted sender) client-ip=209.85.215.46; Received: by mail-la0-f46.google.com with SMTP id hs14so772489lab.19 for ; Tue, 04 Nov 2014 04:33:53 -0800 (PST) X-Received: by 10.152.87.98 with SMTP id w2mr58245793laz.27.1415104433650; Tue, 04 Nov 2014 04:33:53 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.184.201 with SMTP id ew9csp107500lbc; Tue, 4 Nov 2014 04:33:52 -0800 (PST) X-Received: by 10.224.112.2 with SMTP id u2mr5417740qap.14.1415104432395; Tue, 04 Nov 2014 04:33:52 -0800 (PST) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id w2si539936qab.9.2014.11.04.04.33.48 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 04 Nov 2014 04:33:52 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:40182 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XldIy-0005nQ-4y for patch@linaro.org; Tue, 04 Nov 2014 07:33:48 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50105) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XldFy-00011S-Fe for qemu-devel@nongnu.org; Tue, 04 Nov 2014 07:30:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XldFt-0005Pw-LP for qemu-devel@nongnu.org; Tue, 04 Nov 2014 07:30:42 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:54352) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XldFt-0005OQ-2e for qemu-devel@nongnu.org; Tue, 04 Nov 2014 07:30:37 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XldFi-0002mF-Lo for qemu-devel@nongnu.org; Tue, 04 Nov 2014 12:30:26 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 4 Nov 2014 12:30:22 +0000 Message-Id: <1415104226-10638-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1415104226-10638-1-git-send-email-peter.maydell@linaro.org> References: <1415104226-10638-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 3/7] target-arm/translate.c: Don't use IS_M() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.46 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Instead of using IS_M(), use arm_dc_feature(s, ARM_FEATURE_M), so we don't need to pass CPUARMState pointers around the decoder. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Message-id: 1414524244-20316-4-git-send-email-peter.maydell@linaro.org Reviewed-by: Claudio Fontana --- target-arm/translate.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 6811744..64a1bd9 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7574,8 +7574,9 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) s->pc += 4; /* M variants do not implement ARM mode. */ - if (IS_M(env)) + if (arm_dc_feature(s, ARM_FEATURE_M)) { goto illegal_op; + } cond = insn >> 28; if (cond == 0xf){ /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we @@ -9300,7 +9301,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw /* Load/store multiple, RFE, SRS. */ if (((insn >> 23) & 1) == ((insn >> 24) & 1)) { /* RFE, SRS: not available in user mode or on M profile */ - if (IS_USER(s) || IS_M(env)) { + if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) { goto illegal_op; } if (insn & (1 << 20)) { @@ -9804,7 +9805,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw op = (insn >> 20) & 7; switch (op) { case 0: /* msr cpsr. */ - if (IS_M(env)) { + if (arm_dc_feature(s, ARM_FEATURE_M)) { tmp = load_reg(s, rn); addr = tcg_const_i32(insn & 0xff); gen_helper_v7m_msr(cpu_env, addr, tmp); @@ -9815,8 +9816,9 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw } /* fall through */ case 1: /* msr spsr. */ - if (IS_M(env)) + if (arm_dc_feature(s, ARM_FEATURE_M)) { goto illegal_op; + } tmp = load_reg(s, rn); if (gen_set_psr(s, msr_mask(env, s, (insn >> 8) & 0xf, op == 1), @@ -9884,7 +9886,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw break; case 6: /* mrs cpsr. */ tmp = tcg_temp_new_i32(); - if (IS_M(env)) { + if (arm_dc_feature(s, ARM_FEATURE_M)) { addr = tcg_const_i32(insn & 0xff); gen_helper_v7m_mrs(tmp, cpu_env, addr); tcg_temp_free_i32(addr); @@ -9895,8 +9897,9 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw break; case 7: /* mrs spsr. */ /* Not accessible in user mode. */ - if (IS_USER(s) || IS_M(env)) + if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) { goto illegal_op; + } tmp = load_cpu_field(spsr); store_reg(s, rd, tmp); break; @@ -10851,7 +10854,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) if (IS_USER(s)) { break; } - if (IS_M(env)) { + if (arm_dc_feature(s, ARM_FEATURE_M)) { tmp = tcg_const_i32((insn & (1 << 4)) != 0); /* FAULTMASK */ if (insn & 1) { @@ -11123,7 +11126,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, break; } #else - if (dc->pc >= 0xfffffff0 && IS_M(env)) { + if (dc->pc >= 0xfffffff0 && arm_dc_feature(dc, ARM_FEATURE_M)) { /* We always get here via a jump, so know we are not in a conditional execution block. */ gen_exception_internal(EXCP_EXCEPTION_EXIT);