From patchwork Tue Nov 4 12:30:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 40145 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-lb0-f198.google.com (mail-lb0-f198.google.com [209.85.217.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 9F512240A6 for ; Tue, 4 Nov 2014 12:33:56 +0000 (UTC) Received: by mail-lb0-f198.google.com with SMTP id 10sf616505lbg.5 for ; Tue, 04 Nov 2014 04:33:55 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=4PL0H6WNx4zI/3tgR0u+TU3WkcXYNZ9f10DeFzrFk4Q=; b=eNZfF2rr1koBB9oia9mKqbQ2cI+HYugTOFRe65posWJpKQX5n/NjClDQbksd3nfl7S sKoGDG9ZwaA5Q1IC8/d6fV1m39odP68BFf8BtZoAUeou30mEBfiMPbiD90YppSK5x7b8 4lroWjhm4s2OY9KO8SQ34zu7zipQYKpA5NJbzZC8vA7ODanmJccbopmsO5dh3HZYqmb5 J8TIzAta0oXbZRtMZvngntGl0fakJ5yCL+2DwNGqnSZ8xmTwNY62ztcFzpecyQfzEu3P PhBUbmr06laeUjDSb2L3zQyH3ZJwv5gabBbp/W3It2LJPYCMxXmuUuQuA/yiTAcWd/M8 vDKw== X-Gm-Message-State: ALoCoQl/u1DucMMUq7+CTA/EGIMdc0xW5kyZpWgPD9IwjPvZAUiig++zgr5uTqEz54BMJfCyAd9W X-Received: by 10.180.81.5 with SMTP id v5mr1928342wix.0.1415104435444; Tue, 04 Nov 2014 04:33:55 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.153.4.33 with SMTP id cb1ls943415lad.89.gmail; Tue, 04 Nov 2014 04:33:55 -0800 (PST) X-Received: by 10.112.16.39 with SMTP id c7mr58301197lbd.19.1415104435283; Tue, 04 Nov 2014 04:33:55 -0800 (PST) Received: from mail-la0-f43.google.com (mail-la0-f43.google.com. [209.85.215.43]) by mx.google.com with ESMTPS id q1si559329laj.42.2014.11.04.04.33.55 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 04 Nov 2014 04:33:55 -0800 (PST) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.43 as permitted sender) client-ip=209.85.215.43; Received: by mail-la0-f43.google.com with SMTP id ge10so789913lab.16 for ; Tue, 04 Nov 2014 04:33:55 -0800 (PST) X-Received: by 10.152.5.38 with SMTP id p6mr58381367lap.44.1415104434841; Tue, 04 Nov 2014 04:33:54 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.184.201 with SMTP id ew9csp107502lbc; Tue, 4 Nov 2014 04:33:53 -0800 (PST) X-Received: by 10.229.107.136 with SMTP id b8mr75231936qcp.6.1415104432425; Tue, 04 Nov 2014 04:33:52 -0800 (PST) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 2si356923qgx.106.2014.11.04.04.33.48 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 04 Nov 2014 04:33:52 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:40181 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XldIy-0005mR-4u for patch@linaro.org; Tue, 04 Nov 2014 07:33:48 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50057) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XldFu-000111-GA for qemu-devel@nongnu.org; Tue, 04 Nov 2014 07:30:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XldFs-0005PQ-02 for qemu-devel@nongnu.org; Tue, 04 Nov 2014 07:30:38 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:54352) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XldFr-0005OQ-Nw for qemu-devel@nongnu.org; Tue, 04 Nov 2014 07:30:35 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XldFi-0002mR-Qv for qemu-devel@nongnu.org; Tue, 04 Nov 2014 12:30:26 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 4 Nov 2014 12:30:25 +0000 Message-Id: <1415104226-10638-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1415104226-10638-1-git-send-email-peter.maydell@linaro.org> References: <1415104226-10638-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 6/7] target-arm: Separate out M profile cpu_exec_interrupt handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.43 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 The M profile cpu_exec_interrupt handling is fairly simple but does include an M profile specific oddity (disabling interrupts for certain PC values). A/R profile handling on the other hand is getting rapidly more complicated with the support for EL2 and EL3. Split the M profile code out into its own implementation of cpu_exec_interrupt to keep these two things out of each others' way. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Message-id: 1414684132-23971-2-git-send-email-peter.maydell@linaro.org --- target-arm/cpu.c | 49 +++++++++++++++++++++++++++++++++++++++---------- target-arm/cpu.h | 16 ++-------------- 2 files changed, 41 insertions(+), 24 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index e0b82a6..5ce7350 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -203,15 +203,6 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) cc->do_interrupt(cs); ret = true; } - /* ARMv7-M interrupt return works by loading a magic value - into the PC. On real hardware the load causes the - return to occur. The qemu implementation performs the - jump normally, then does the exception return when the - CPU tries to execute code at the magic address. - This will cause the magic PC value to be pushed to - the stack if an interrupt occurred at the wrong time. - We avoid this by disabling interrupts when - pc contains a magic address. */ if (interrupt_request & CPU_INTERRUPT_HARD && arm_excp_unmasked(cs, EXCP_IRQ)) { cs->exception_index = EXCP_IRQ; @@ -234,6 +225,42 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return ret; } +#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) +static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + CPUClass *cc = CPU_GET_CLASS(cs); + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + bool ret = false; + + + if (interrupt_request & CPU_INTERRUPT_FIQ + && !(env->daif & PSTATE_F)) { + cs->exception_index = EXCP_FIQ; + cc->do_interrupt(cs); + ret = true; + } + /* ARMv7-M interrupt return works by loading a magic value + * into the PC. On real hardware the load causes the + * return to occur. The qemu implementation performs the + * jump normally, then does the exception return when the + * CPU tries to execute code at the magic address. + * This will cause the magic PC value to be pushed to + * the stack if an interrupt occurred at the wrong time. + * We avoid this by disabling interrupts when + * pc contains a magic address. + */ + if (interrupt_request & CPU_INTERRUPT_HARD + && !(env->daif & PSTATE_I) + && (env->regs[15] < 0xfffffff0)) { + cs->exception_index = EXCP_IRQ; + cc->do_interrupt(cs); + ret = true; + } + return ret; +} +#endif + #ifndef CONFIG_USER_ONLY static void arm_cpu_set_irq(void *opaque, int irq, int level) { @@ -670,11 +697,13 @@ static void cortex_m3_initfn(Object *obj) static void arm_v7m_class_init(ObjectClass *oc, void *data) { -#ifndef CONFIG_USER_ONLY CPUClass *cc = CPU_CLASS(oc); +#ifndef CONFIG_USER_ONLY cc->do_interrupt = arm_v7m_cpu_do_interrupt; #endif + + cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; } static const ARMCPRegInfo cortexa8_cp_reginfo[] = { diff --git a/target-arm/cpu.h b/target-arm/cpu.h index cb6ec5c..97eaf79 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1251,18 +1251,6 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) bool secure = false; /* If in EL1/0, Physical IRQ routing to EL2 only happens from NS state. */ bool irq_can_hyp = !secure && cur_el < 2 && target_el == 2; - /* ARMv7-M interrupt return works by loading a magic value - * into the PC. On real hardware the load causes the - * return to occur. The qemu implementation performs the - * jump normally, then does the exception return when the - * CPU tries to execute code at the magic address. - * This will cause the magic PC value to be pushed to - * the stack if an interrupt occurred at the wrong time. - * We avoid this by disabling interrupts when - * pc contains a magic address. - */ - bool irq_unmasked = !(env->daif & PSTATE_I) - && (!IS_M(env) || env->regs[15] < 0xfffffff0); /* Don't take exceptions if they target a lower EL. */ if (cur_el > target_el) { @@ -1279,7 +1267,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_IMO)) { return true; } - return irq_unmasked; + return !(env->daif & PSTATE_I); case EXCP_VFIQ: if (!secure && !(env->cp15.hcr_el2 & HCR_FMO)) { /* VFIQs are only taken when hypervized and non-secure. */ @@ -1291,7 +1279,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) /* VIRQs are only taken when hypervized and non-secure. */ return false; } - return irq_unmasked; + return !(env->daif & PSTATE_I); default: g_assert_not_reached(); }