From patchwork Mon Nov 17 16:47:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 40939 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f198.google.com (mail-wi0-f198.google.com [209.85.212.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 0E1B224035 for ; Mon, 17 Nov 2014 16:49:49 +0000 (UTC) Received: by mail-wi0-f198.google.com with SMTP id r20sf1201023wiv.1 for ; Mon, 17 Nov 2014 08:49:48 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=CJDUeNjSLCjRt6i8bs/THs3VdQvD1XbJfhrYCP1jeSU=; b=QAQkhfXyQy2pXaOWfu5vdpkcQdv1EzGGlIvVqFwTJAQkIzS8u0tbsr7O/nyYknOH8a WaZ99CFtJEKcGtFBQd1whIYZ63ZRjXjBDPX88V3bOeIb4UIM6fVSF+3omAOFqYCqFsBn nIZDC4oIiOhgsLImuo5FynxlF/wIdUcmxcP9foXyWq54d+6wIWJhHidcubiSFCyaYQoa Cd7QegIvpo3EHFQ5JTBrmyEdZht52Q+BMssBDdcswhdJ3Sa8rPEhIwd9o/A/XjWpxSS3 XQr0PNzgIiRoXgLQfEHpVUb/A+TX9rDLRu5mXBLKRQnooruE1i/M+vKKTPD1V6gFxs7T L6kA== X-Gm-Message-State: ALoCoQnWvo9ByHiBDezU22Ge9/o7MjFVRa2HzfXHgCtgz/4lsrQQyxiWmiyl61ocneY2HxWlg8vO X-Received: by 10.112.29.52 with SMTP id g20mr8984194lbh.7.1416242988263; Mon, 17 Nov 2014 08:49:48 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.2.168 with SMTP id 8ls123181lav.47.gmail; Mon, 17 Nov 2014 08:49:48 -0800 (PST) X-Received: by 10.152.204.9 with SMTP id ku9mr14600262lac.55.1416242988018; Mon, 17 Nov 2014 08:49:48 -0800 (PST) Received: from mail-lb0-f173.google.com (mail-lb0-f173.google.com. [209.85.217.173]) by mx.google.com with ESMTPS id qi2si52618629lbb.47.2014.11.17.08.49.47 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 17 Nov 2014 08:49:48 -0800 (PST) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.173 as permitted sender) client-ip=209.85.217.173; Received: by mail-lb0-f173.google.com with SMTP id n15so16495632lbi.18 for ; Mon, 17 Nov 2014 08:49:47 -0800 (PST) X-Received: by 10.152.6.228 with SMTP id e4mr11984510laa.71.1416242987893; Mon, 17 Nov 2014 08:49:47 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.184.201 with SMTP id ew9csp1186935lbc; Mon, 17 Nov 2014 08:49:47 -0800 (PST) X-Received: by 10.229.214.5 with SMTP id gy5mr35725823qcb.18.1416242986004; Mon, 17 Nov 2014 08:49:46 -0800 (PST) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id j61si5736745qgj.88.2014.11.17.08.49.45 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 17 Nov 2014 08:49:45 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:48837 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPUn-0002z4-6v for patch@linaro.org; Mon, 17 Nov 2014 11:49:45 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59843) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPTW-0001PH-6S for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:48:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XqPTR-0007AT-E7 for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:48:26 -0500 Received: from mail-pa0-f49.google.com ([209.85.220.49]:41771) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPTR-00079n-97 for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:48:21 -0500 Received: by mail-pa0-f49.google.com with SMTP id eu11so817451pac.36 for ; Mon, 17 Nov 2014 08:48:20 -0800 (PST) X-Received: by 10.68.203.41 with SMTP id kn9mr30539401pbc.47.1416242900714; Mon, 17 Nov 2014 08:48:20 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id r2sm18499056pdi.60.2014.11.17.08.48.19 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 17 Nov 2014 08:48:20 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Mon, 17 Nov 2014 10:47:40 -0600 Message-Id: <1416242878-876-9-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1416242878-876-1-git-send-email-greg.bellows@linaro.org> References: <1416242878-876-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.49 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v11 08/26] target-arm: move AArch32 SCR into security reglist X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.173 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler Define a new ARM CP register info list for the ARMv7 Security Extension feature. Register that list only for ARM cores with Security Extension/EL3 support. Moving AArch32 SCR into Security Extension register group. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v7 -> v8 - Fix SCR register fieldoffset to be offsetoflow32. - Rename v7_el3_cp_reginfo to el3_cp_reginfo and remove v7 feature check when defining. This allows all common v7/8 secure CP regs to be registered together leaving the v8_el3_cp_reginfo to only v8 specific EL3 registers. - Move SCR_EL3 into el3_cp_reginfo. v4 -> v5 - Added reset value on SCR_EL3 - Squashed SCR Migration fix (previously patch 33) This patch adds code to mark duplicate CP register registrations as NO_MIGRATE to avoid duplicate migrations. v3 -> v4 - Renamed security_cp_reginfo to v7_el3_cp_reginfo - Conditionalized define on whether v7 or v8 were enabled --- target-arm/helper.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 9a1915b5..6c4b467 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -898,9 +898,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .access = PL1_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), .resetvalue = 0 }, - { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), - .resetvalue = 0, .writefn = scr_write }, { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, @@ -2335,11 +2332,18 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { .access = PL3_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), .resetvalue = 0 }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo el3_cp_reginfo[] = { { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, - .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), - .writefn = scr_write }, + .resetvalue = 0, .writefn = scr_write }, + { .name = "SCR", .type = ARM_CP_NO_MIGRATE, + .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, + .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), + .resetfn = arm_cp_reset_ignore, .writefn = scr_write }, REGINFO_SENTINEL }; @@ -2960,7 +2964,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) } } if (arm_feature(env, ARM_FEATURE_EL3)) { - define_arm_cp_regs(cpu, v8_el3_cp_reginfo); + if (arm_feature(env, ARM_FEATURE_V8)) { + define_arm_cp_regs(cpu, v8_el3_cp_reginfo); + } + define_arm_cp_regs(cpu, el3_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_MPU)) { /* These are the MPU registers prior to PMSAv6. Any new