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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id qn8si3362544pab.101.2014.12.09.11.46.32 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 09 Dec 2014 11:46:34 -0800 (PST) Received-SPF: none (google.com: pm215@archaic.org.uk does not designate permitted sender hosts) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XyQjr-0005dU-5h; Tue, 09 Dec 2014 19:46:27 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Christoffer Dall , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH 2/2] target-arm: Add checks that cpreg raw accesses are handled Date: Tue, 9 Dec 2014 19:46:27 +0000 Message-Id: <1418154387-21631-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1418154387-21631-1-git-send-email-peter.maydell@linaro.org> References: <1418154387-21631-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add assertion checking when cpreg structures are registered that they either forbid raw-access attempts or at least make an attempt at handling them. Also add an assert in the raw-accessor-of-last-resort, to avoid silently doing a read or write from offset zero, which is actually AArch32 CPU register r0. Signed-off-by: Peter Maydell --- target-arm/helper.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index d1b856c..99a092c 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -119,6 +119,7 @@ static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) { + assert(ri->fieldoffset); if (cpreg_field_is_64bit(ri)) { return CPREG_FIELD64(env, ri); } else { @@ -129,6 +130,7 @@ static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + assert(ri->fieldoffset); if (cpreg_field_is_64bit(ri)) { CPREG_FIELD64(env, ri) = value; } else { @@ -174,6 +176,18 @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, } } +static bool raw_accessors_valid(const ARMCPRegInfo *ri) +{ + /* Return true if a raw access on this register is OK (ie will not + * fall into the assert in raw_read() or raw_write()) + */ + if (ri->type & ARM_CP_CONST) { + return true; + } + return (ri->raw_writefn || ri->writefn || ri->fieldoffset) && + (ri->raw_readfn || ri->readfn || ri->fieldoffset); +} + bool write_cpustate_to_list(ARMCPU *cpu) { /* Write the coprocessor state from cpu->env to the (index,value) list. */ @@ -3516,6 +3530,14 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, r2->type |= ARM_CP_ALIAS; } + /* Check that raw accesses are either forbidden or handled. Note that + * we can't assert this earlier because the setup of fieldoffset for + * banked registers has to be done first. + */ + if (!(r2->type & ARM_CP_NO_RAW)) { + assert(raw_accessors_valid(r2)); + } + /* Overriding of an existing definition must be explicitly * requested. */