From patchwork Thu Dec 11 12:19:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 42134 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ee0-f72.google.com (mail-ee0-f72.google.com [74.125.83.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 7E87A26C6D for ; Thu, 11 Dec 2014 12:30:30 +0000 (UTC) Received: by mail-ee0-f72.google.com with SMTP id e53sf3630552eek.7 for ; Thu, 11 Dec 2014 04:30:29 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=htmAdENEsVsZ44kDcVjJcW8/2LBhD1j7zT7VS2KQcr8=; b=UQUkBmZhntKd6vwP7bdObMFFELcnITSZ5SJA4USaFf2BYu8gsd2TyNSX0TTgY5aIIu YVeP9RVwBGtrhk4yUz/YB+4lfzJ2MDxzf0O/G0QC40yfgXiiy0PNVjUs7OgtnAvueOqh uzKcCNfU/ElyaETxn+gVUR87l0MAxsbYcDjHaxZd1yxjOOoZ0rsBysUiLNVBa5QP+dCe ECCh8xbNjJeb2zOYI92kUgc5dNHSD3VVuUPzOWiqnvyXrmQQpdoPqQILeXS6FzLCxWrU D8NM6Spdiy2E0wfdacem2ln5BvzDfurquFSXhtKHGqAlfdj/4bF93pYvTaA6SMutSoCf m18w== X-Gm-Message-State: ALoCoQmLi57x+aDLREYv/agNjWB8lq3Jrlv3+vPXikhW9ECE8uNRgevD0yQLO+c929Vd1+WxOFtQ X-Received: by 10.194.71.48 with SMTP id r16mr7715wju.7.1418301029716; Thu, 11 Dec 2014 04:30:29 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.234.228 with SMTP id uh4ls299220lac.108.gmail; Thu, 11 Dec 2014 04:30:29 -0800 (PST) X-Received: by 10.112.63.133 with SMTP id g5mr9558330lbs.33.1418301029560; Thu, 11 Dec 2014 04:30:29 -0800 (PST) Received: from mail-lb0-f175.google.com (mail-lb0-f175.google.com. [209.85.217.175]) by mx.google.com with ESMTPS id ld3si1097845lac.115.2014.12.11.04.30.29 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 11 Dec 2014 04:30:29 -0800 (PST) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.175 as permitted sender) client-ip=209.85.217.175; Received: by mail-lb0-f175.google.com with SMTP id u10so3967283lbd.6 for ; Thu, 11 Dec 2014 04:30:29 -0800 (PST) X-Received: by 10.112.131.1 with SMTP id oi1mr2350432lbb.2.1418301029448; Thu, 11 Dec 2014 04:30:29 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.142.69 with SMTP id ru5csp506174lbb; Thu, 11 Dec 2014 04:30:28 -0800 (PST) X-Received: by 10.140.39.5 with SMTP id u5mr18265595qgu.28.1418301027822; Thu, 11 Dec 2014 04:30:27 -0800 (PST) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id f3si1070771qcg.36.2014.12.11.04.30.27 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 11 Dec 2014 04:30:27 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:50606 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xz2t0-0004si-Oz for patch@linaro.org; Thu, 11 Dec 2014 07:30:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44687) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xz2j6-00054q-PD for qemu-devel@nongnu.org; Thu, 11 Dec 2014 07:20:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xz2j1-0007Ru-U1 for qemu-devel@nongnu.org; Thu, 11 Dec 2014 07:20:12 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:54567) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xz2j1-0006sg-Ij for qemu-devel@nongnu.org; Thu, 11 Dec 2014 07:20:07 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Xz2iq-0001AC-E3 for qemu-devel@nongnu.org; Thu, 11 Dec 2014 12:19:56 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 11 Dec 2014 12:19:42 +0000 Message-Id: <1418300395-4348-21-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1418300395-4348-1-git-send-email-peter.maydell@linaro.org> References: <1418300395-4348-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 20/33] target-arm: make DACR banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler When EL3 is running in AArch32 (or ARMv7 with Security Extensions) DACR has a secure and a non-secure instance. Adds definition for DACR32_EL2. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell Message-id: 1416242878-876-19-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell --- hw/arm/pxa2xx.c | 2 +- target-arm/cpu.h | 13 +++++++++++-- target-arm/helper.c | 28 ++++++++++++++++++---------- 3 files changed, 30 insertions(+), 13 deletions(-) diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 2b00b59..8967cc4 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -276,7 +276,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, s->cpu->env.cp15.sctlr_ns = 0; s->cpu->env.cp15.c1_coproc = 0; s->cpu->env.cp15.ttbr0_el[1] = 0; - s->cpu->env.cp15.c3 = 0; + s->cpu->env.cp15.dacr_ns = 0; s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 0eaf981..1906fc1 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -227,8 +227,17 @@ typedef struct CPUARMState { TCR tcr_el[4]; uint32_t c2_data; /* MPU data cachable bits. */ uint32_t c2_insn; /* MPU instruction cachable bits. */ - uint32_t c3; /* MMU domain access control register - MPU write buffer control. */ + union { /* MMU domain access control register + * MPU write buffer control. + */ + struct { + uint64_t dacr_ns; + uint64_t dacr_s; + }; + struct { + uint64_t dacr32_el2; + }; + }; uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ uint64_t hcr_el2; /* Hypervisor configuration register */ diff --git a/target-arm/helper.c b/target-arm/helper.c index b80608c..ad9481c 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -440,10 +440,12 @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = { * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). */ /* MMU Domain access control / MPU write buffer control */ - { .name = "DACR", .cp = 15, - .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3), - .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, }, + { .name = "DACR", + .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, + .access = PL1_RW, .resetvalue = 0, + .writefn = dacr_write, .raw_writefn = raw_write, + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), + offsetoflow32(CPUARMState, cp15.dacr_ns) } }, /* ??? This covers not just the impdef TLB lockdown registers but also * some v7VMSA registers relating to TEX remap, so it is overly broad. */ @@ -2257,10 +2259,11 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, .type = ARM_CP_NOP, .access = PL1_W }, /* MMU Domain access control / MPU write buffer control */ - { .name = "DACR", .cp = 15, - .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3), - .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, }, + { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, + .access = PL1_RW, .resetvalue = 0, + .writefn = dacr_write, .raw_writefn = raw_write, + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), + offsetoflow32(CPUARMState, cp15.dacr_ns) } }, { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, @@ -2330,6 +2333,11 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), .writefn = hcr_write }, + { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, + .access = PL2_RW, .resetvalue = 0, + .writefn = dacr_write, .raw_writefn = raw_write, + .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, @@ -4517,7 +4525,7 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type, desc = ldl_phys(cs->as, table); type = (desc & 3); domain = (desc >> 5) & 0x0f; - domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; + domain_prot = (A32_BANKED_CURRENT_REG_GET(env, dacr) >> (domain * 2)) & 3; if (type == 0) { /* Section translation fault. */ code = 5; @@ -4629,7 +4637,7 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type, /* Page or Section. */ domain = (desc >> 5) & 0x0f; } - domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; + domain_prot = (A32_BANKED_CURRENT_REG_GET(env, dacr) >> (domain * 2)) & 3; if (domain_prot == 0 || domain_prot == 2) { if (type != 1) { code = 9; /* Section domain fault. */