From patchwork Thu Dec 11 23:29:29 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 42166 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ee0-f72.google.com (mail-ee0-f72.google.com [74.125.83.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id C7A1626666 for ; Thu, 11 Dec 2014 23:34:58 +0000 (UTC) Received: by mail-ee0-f72.google.com with SMTP id e53sf4468120eek.11 for ; Thu, 11 Dec 2014 15:34:57 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=jfUSZv0WUTnbcNaEy0phlMExfGhSe6pTGGPaqHXzSkQ=; b=JN5K8liIIO4NhJdJa4911qHSRRoqKJ60zaVcWX3vStTcGgyeikYc1lSTYT2Hhb8T0G +Jh6zm1X7g6d5eynF4Kb4AxEBTcA0VFlq1ADA09gEQ1TALWKSWqpqRkxQDfCWujuKoh8 uG16HrC+OlU+ll26kY0el+xtgggIj/tANwrqbLngrLSf7ROLRjYrg8rvO/4LA9989uQt 3Bs9/d1ajmfIho+kgmXg2LzHgOWFFYMWTCHGlbYkIwk49tn45emH5g7KoSWVQzb0JXQc hh6tM+JnevMaW2Y+jVgcGHqZaHjdnhenIqj4XIDaimwYPEahISJA75sB1xQA5eaEGmD9 cycw== X-Gm-Message-State: ALoCoQlOdWhMjLyNo9+x7dkiUYdKciP2hgotnb6HmOp3Ic51V0rGU7mYssa5woFbkir3vxAG3LzP X-Received: by 10.112.169.101 with SMTP id ad5mr2082940lbc.1.1418340897794; Thu, 11 Dec 2014 15:34:57 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.153.6.5 with SMTP id cq5ls370843lad.93.gmail; Thu, 11 Dec 2014 15:34:57 -0800 (PST) X-Received: by 10.112.141.42 with SMTP id rl10mr12419785lbb.98.1418340897459; Thu, 11 Dec 2014 15:34:57 -0800 (PST) Received: from mail-la0-f45.google.com (mail-la0-f45.google.com. [209.85.215.45]) by mx.google.com with ESMTPS id cj9si2703608lad.108.2014.12.11.15.34.57 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 11 Dec 2014 15:34:57 -0800 (PST) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.45 as permitted sender) client-ip=209.85.215.45; Received: by mail-la0-f45.google.com with SMTP id gq15so5271183lab.18 for ; Thu, 11 Dec 2014 15:34:57 -0800 (PST) X-Received: by 10.112.162.106 with SMTP id xz10mr12503511lbb.91.1418340897377; Thu, 11 Dec 2014 15:34:57 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.142.69 with SMTP id ru5csp686855lbb; Thu, 11 Dec 2014 15:34:56 -0800 (PST) X-Received: by 10.224.137.198 with SMTP id x6mr25393449qat.11.1418340896018; Thu, 11 Dec 2014 15:34:56 -0800 (PST) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id o88si3252911qga.12.2014.12.11.15.34.55 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 11 Dec 2014 15:34:56 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:54673 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzDG3-0003cU-1G for patch@linaro.org; Thu, 11 Dec 2014 18:34:55 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57600) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzDBT-0004HE-4c for qemu-devel@nongnu.org; Thu, 11 Dec 2014 18:30:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XzDBN-0001Hy-Qu for qemu-devel@nongnu.org; Thu, 11 Dec 2014 18:30:10 -0500 Received: from mail-pd0-f176.google.com ([209.85.192.176]:39400) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzDBN-0001Fj-F4 for qemu-devel@nongnu.org; Thu, 11 Dec 2014 18:30:05 -0500 Received: by mail-pd0-f176.google.com with SMTP id r10so3955336pdi.21 for ; Thu, 11 Dec 2014 15:30:05 -0800 (PST) X-Received: by 10.70.92.100 with SMTP id cl4mr21235226pdb.151.1418340604893; Thu, 11 Dec 2014 15:30:04 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id ip1sm2362908pbc.0.2014.12.11.15.30.02 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 11 Dec 2014 15:30:03 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Thu, 11 Dec 2014 17:29:29 -0600 Message-Id: <1418340569-30519-16-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1418340569-30519-1-git-send-email-greg.bellows@linaro.org> References: <1418340569-30519-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.176 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH v2 15/15] target-arm: add cpu feature EL3 to CPUs with Security Extensions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.45 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- target-arm/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 758e8f8..cb89ee2 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -669,6 +669,7 @@ static void arm1176_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr = 0x410fb767; cpu->reset_fpsid = 0x410120b5; cpu->mvfr0 = 0x11111111; @@ -757,6 +758,7 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr = 0x410fc080; cpu->reset_fpsid = 0x410330c0; cpu->mvfr0 = 0x11110222; @@ -824,6 +826,7 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_EL3); /* Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different * and valid configurations; we don't model A9UP). @@ -891,6 +894,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_LPAE); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; cpu->midr = 0x412fc0f1; cpu->reset_fpsid = 0x410430f0;