From patchwork Thu Feb 5 14:02:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 44430 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f199.google.com (mail-wi0-f199.google.com [209.85.212.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 5E78021521 for ; Thu, 5 Feb 2015 14:04:41 +0000 (UTC) Received: by mail-wi0-f199.google.com with SMTP id r20sf6536150wiv.2 for ; Thu, 05 Feb 2015 06:04:40 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=nlwIYlCx4wc7ZzJ4PYvsSjjQtSh1Ns+cIShlxLigNx4=; b=V/KhRUqTzOxeNyo1LsfoI/lFKS+8lrgaNicjhzCYEQheSUQsL5PbNzHVs/uSB0gtJf nfnwnOM6NcIjRqFPBmCumILt5rsOjxjAxtKgsx4WycO4o664h2wKWNM7Nj2dLvPl5WBD xZbRXcVS4aL/hSBnXWrFYBvZHHCd0lxyf9f9Q0GR/hnIwkdulRSEazU5bnRy9BT3974Z E+5VpbgGbdomnOgb0xL8S6v40wI+f0xHoInjr6c6zXjiM6/P+YBwdIvXdAZXtDpxR5KV 2YYgQyVxqMANEF4yAcUIlA7ragCEXnZ6Juw39CmFSOqA+nu44PRlEUK36nzIo0RaTKOr 3TxA== X-Gm-Message-State: ALoCoQnHZRYDcAV/m0rzbggGhIRAnaqLaNtE9hLItAQoN4W4A6EICbYvQOTatMNHlbIZFqJLKpc0 X-Received: by 10.180.98.131 with SMTP id ei3mr1074244wib.5.1423145080698; Thu, 05 Feb 2015 06:04:40 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.9.9 with SMTP id v9ls150572laa.34.gmail; Thu, 05 Feb 2015 06:04:40 -0800 (PST) X-Received: by 10.152.29.198 with SMTP id m6mr181118lah.102.1423145080466; Thu, 05 Feb 2015 06:04:40 -0800 (PST) Received: from mail-lb0-f170.google.com (mail-lb0-f170.google.com. [209.85.217.170]) by mx.google.com with ESMTPS id r14si4056309lal.15.2015.02.05.06.04.40 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Feb 2015 06:04:40 -0800 (PST) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.170 as permitted sender) client-ip=209.85.217.170; Received: by mail-lb0-f170.google.com with SMTP id w7so7493830lbi.1 for ; Thu, 05 Feb 2015 06:04:40 -0800 (PST) X-Received: by 10.152.43.193 with SMTP id y1mr331888lal.35.1423145079994; Thu, 05 Feb 2015 06:04:39 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.35.133 with SMTP id h5csp1160076lbj; Thu, 5 Feb 2015 06:04:39 -0800 (PST) X-Received: by 10.224.79.82 with SMTP id o18mr8417148qak.3.1423145075649; Thu, 05 Feb 2015 06:04:35 -0800 (PST) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id a3si6231031qas.19.2015.02.05.06.04.35 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 05 Feb 2015 06:04:35 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:42100 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YJN2o-0002ZA-QR for patch@linaro.org; Thu, 05 Feb 2015 09:04:34 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49665) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YJN1Z-0001OO-JI for qemu-devel@nongnu.org; Thu, 05 Feb 2015 09:03:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YJN1Y-0007Sk-6D for qemu-devel@nongnu.org; Thu, 05 Feb 2015 09:03:17 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:54955) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YJN1X-0007RD-TV for qemu-devel@nongnu.org; Thu, 05 Feb 2015 09:03:16 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1YJN1P-0002yo-B7 for qemu-devel@nongnu.org; Thu, 05 Feb 2015 14:03:07 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 5 Feb 2015 14:02:40 +0000 Message-Id: <1423144987-11425-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1423144987-11425-1-git-send-email-peter.maydell@linaro.org> References: <1423144987-11425-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 01/28] target_arm: Remove memory region init from armv7m_init X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.170 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Alistair Francis This patch moves the memory region init code from the armv7m_init function to the stellaris_init function Signed-off-by: Alistair Francis Reviewed-by: Peter Crosthwaite Message-id: 4836be7e1d708554d6eb0bc639dc2fbf7dac0458.1422077994.git.alistair23@gmail.com Signed-off-by: Peter Maydell --- hw/arm/armv7m.c | 33 +++------------------------------ hw/arm/stellaris.c | 24 ++++++++++++++++++++---- include/hw/arm/arm.h | 3 +-- 3 files changed, 24 insertions(+), 36 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index ef24ca4..50281f7 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -163,11 +163,10 @@ static void armv7m_reset(void *opaque) } /* Init CPU and memory for a v7-M based board. - flash_size and sram_size are in kb. + mem_size is in bytes. Returns the NVIC array. */ -qemu_irq *armv7m_init(MemoryRegion *system_memory, - int flash_size, int sram_size, +qemu_irq *armv7m_init(MemoryRegion *system_memory, int mem_size, const char *kernel_filename, const char *cpu_model) { ARMCPU *cpu; @@ -180,13 +179,8 @@ qemu_irq *armv7m_init(MemoryRegion *system_memory, uint64_t lowaddr; int i; int big_endian; - MemoryRegion *sram = g_new(MemoryRegion, 1); - MemoryRegion *flash = g_new(MemoryRegion, 1); MemoryRegion *hack = g_new(MemoryRegion, 1); - flash_size *= 1024; - sram_size *= 1024; - if (cpu_model == NULL) { cpu_model = "cortex-m3"; } @@ -197,27 +191,6 @@ qemu_irq *armv7m_init(MemoryRegion *system_memory, } env = &cpu->env; -#if 0 - /* > 32Mb SRAM gets complicated because it overlaps the bitband area. - We don't have proper commandline options, so allocate half of memory - as SRAM, up to a maximum of 32Mb, and the rest as code. */ - if (ram_size > (512 + 32) * 1024 * 1024) - ram_size = (512 + 32) * 1024 * 1024; - sram_size = (ram_size / 2) & TARGET_PAGE_MASK; - if (sram_size > 32 * 1024 * 1024) - sram_size = 32 * 1024 * 1024; - code_size = ram_size - sram_size; -#endif - - /* Flash programming is done via the SCU, so pretend it is ROM. */ - memory_region_init_ram(flash, NULL, "armv7m.flash", flash_size, - &error_abort); - vmstate_register_ram_global(flash); - memory_region_set_readonly(flash, true); - memory_region_add_subregion(system_memory, 0, flash); - memory_region_init_ram(sram, NULL, "armv7m.sram", sram_size, &error_abort); - vmstate_register_ram_global(sram); - memory_region_add_subregion(system_memory, 0x20000000, sram); armv7m_bitband_init(); nvic = qdev_create(NULL, "armv7m_nvic"); @@ -244,7 +217,7 @@ qemu_irq *armv7m_init(MemoryRegion *system_memory, image_size = load_elf(kernel_filename, NULL, NULL, &entry, &lowaddr, NULL, big_endian, ELF_MACHINE, 1); if (image_size < 0) { - image_size = load_image_targphys(kernel_filename, 0, flash_size); + image_size = load_image_targphys(kernel_filename, 0, mem_size); lowaddr = 0; } if (image_size < 0) { diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index ccc3b18..8e9c30b 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1220,10 +1220,26 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model, int i; int j; - flash_size = ((board->dc0 & 0xffff) + 1) << 1; - sram_size = (board->dc0 >> 18) + 1; - pic = armv7m_init(get_system_memory(), - flash_size, sram_size, kernel_filename, cpu_model); + MemoryRegion *sram = g_new(MemoryRegion, 1); + MemoryRegion *flash = g_new(MemoryRegion, 1); + MemoryRegion *system_memory = get_system_memory(); + + flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; + sram_size = ((board->dc0 >> 18) + 1) * 1024; + + /* Flash programming is done via the SCU, so pretend it is ROM. */ + memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size, + &error_abort); + vmstate_register_ram_global(flash); + memory_region_set_readonly(flash, true); + memory_region_add_subregion(system_memory, 0, flash); + + memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, + &error_abort); + vmstate_register_ram_global(sram); + memory_region_add_subregion(system_memory, 0x20000000, sram); + + pic = armv7m_init(system_memory, flash_size, kernel_filename, cpu_model); if (board->dc1 & (1 << 16)) { dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index c4bf56d..f8b329b 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -15,8 +15,7 @@ #include "hw/irq.h" /* armv7m.c */ -qemu_irq *armv7m_init(MemoryRegion *system_memory, - int flash_size, int sram_size, +qemu_irq *armv7m_init(MemoryRegion *system_memory, int mem_size, const char *kernel_filename, const char *cpu_model); /* arm_boot.c */