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[99.179.1.214]) by mx.google.com with ESMTPSA id x142sm2567707oie.19.2015.04.15.09.02.35 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 15 Apr 2015 09:02:36 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 15 Apr 2015 11:02:10 -0500 Message-Id: <1429113742-8371-5-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1429113742-8371-1-git-send-email-greg.bellows@linaro.org> References: <1429113742-8371-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.179 Cc: Fabian Aggeler , Greg Bellows Subject: [Qemu-devel] [PATCH v3 04/16] hw/intc/arm_gic: Add Security Extensions property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler The existing implementation does not support Security Extensions mentioned in the GICv1 and GICv2 architecture specification. Security Extensions are not available on all GICs. This property makes it possible to enable Security Extensions. It also makes GICD_TYPER/ICDICTR.SecurityExtn RAO for GICs which implement Security Extensions. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- v1 -> v2 - Change GICState security extension property from a uint8 type to bool --- hw/intc/arm_gic.c | 5 ++++- hw/intc/arm_gic_common.c | 1 + include/hw/intc/arm_gic_common.h | 1 + 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index e9fb8b9..cdf7408 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -298,7 +298,10 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset) if (offset == 0) return s->enabled; if (offset == 4) - return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5); + /* Interrupt Controller Type Register */ + return ((s->num_irq / 32) - 1) + | ((NUM_CPU(s) - 1) << 5) + | (s->security_extn << 10); if (offset < 0x08) return 0; if (offset >= 0x80) { diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 18b01ba..e35049d 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -149,6 +149,7 @@ static Property arm_gic_common_properties[] = { * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".) */ DEFINE_PROP_UINT32("revision", GICState, revision, 1), + DEFINE_PROP_BOOL("security-extn", GICState, security_extn, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index 01c6f24..7825134 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -105,6 +105,7 @@ typedef struct GICState { MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ uint32_t num_irq; uint32_t revision; + bool security_extn; int dev_fd; /* kvm device fd if backed by kvm vgic support */ } GICState;