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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id 201si485475qhv.50.2015.05.14.02.27.17 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 14 May 2015 02:27:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:53301 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YspQD-0000MQ-6u for patch@linaro.org; Thu, 14 May 2015 05:27:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48216) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YspNW-0005GP-7V for qemu-devel@nongnu.org; Thu, 14 May 2015 05:24:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YspNR-00018r-OH for qemu-devel@nongnu.org; Thu, 14 May 2015 05:24:30 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:32389) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YspNR-00016q-1C for qemu-devel@nongnu.org; Thu, 14 May 2015 05:24:25 -0400 Received: from 172.24.2.119 (EHLO szxeml430-hub.china.huawei.com) ([172.24.2.119]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CLJ60755; Thu, 14 May 2015 17:20:59 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml430-hub.china.huawei.com (10.82.67.185) with Microsoft SMTP Server id 14.3.158.1; Thu, 14 May 2015 17:20:51 +0800 From: Shannon Zhao To: , , , , , , , , , , Date: Thu, 14 May 2015 17:19:24 +0800 Message-ID: <1431595182-7552-6-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1431595182-7552-1-git-send-email-zhaoshenglong@huawei.com> References: <1431595182-7552-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] X-Received-From: 119.145.14.65 Cc: hangaohuai@huawei.com, zhaoshenglong@huawei.com, peter.huangpeng@huawei.com, shannon.zhao@linaro.org Subject: [Qemu-devel] [PATCH v7 05/23] hw/acpi/aml-build: Add aml_interrupt() term X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.41 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Shannon Zhao Add aml_interrupt() for describing device interrupt in resource template. These can be used to generating DSDT table for ACPI on ARM. Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao --- hw/acpi/aml-build.c | 23 +++++++++++++++++++++ include/hw/acpi/aml-build.h | 50 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index ce68d27..7553bfc 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -530,6 +530,29 @@ Aml *aml_memory32_fixed(uint32_t addr, uint32_t size, return var; } +/* + * ACPI 1.0: 6.4.3.6 Interrupt (Interrupt Resource Descriptor Macro) + */ +Aml *aml_interrupt(AmlConsumerAndProducer con_and_pro, + AmlLevelAndEdge level_and_edge, + AmlActiveHighAndLow high_and_low, + AmlExclusiveAndShared exclusive_and_shared, + AmlWakeCap wake_capable, uint32_t irq) +{ + Aml *var = aml_alloc(); + uint8_t irq_flags = con_and_pro | (level_and_edge << 1) + | (high_and_low << 2) | (exclusive_and_shared << 3) + | (wake_capable << 4); + + build_append_byte(var->buf, 0x89); /* Extended irq descriptor */ + build_append_byte(var->buf, 6); /* Length, bits[7:0] minimum value = 6 */ + build_append_byte(var->buf, 0); /* Length, bits[15:8] minimum value = 0 */ + build_append_byte(var->buf, irq_flags); /* Interrupt Vector Information. */ + build_append_byte(var->buf, 0x01); /* Interrupt table length = 1 */ + build_append_uint32(var->buf, irq); /* Interrupt Number */ + return var; +} + /* ACPI 1.0b: 6.4.2.5 I/O Port Descriptor */ Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base, uint8_t aln, uint8_t len) diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index b1413a3..586a742 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -111,6 +111,51 @@ typedef enum { aml_ReadWrite = 1, } AmlReadAndWrite; +/* + * ACPI 1.0b: Table 6-28 Extended Interrupt Descriptor Definition + * Interrupt Vector Flags Bits[0] Consumer/Producer + */ +typedef enum { + aml_consumer_producer = 0, + aml_consumer = 1, +} AmlConsumerAndProducer; + +/* + * ACPI 1.0b: Table 6-28 Extended Interrupt Descriptor Definition + * _HE field definition + */ +typedef enum { + aml_level = 0, + aml_edge = 1, +} AmlLevelAndEdge; + +/* + * ACPI 1.0b: Table 6-28 Extended Interrupt Descriptor Definition + * _LL field definition + */ +typedef enum { + aml_active_high = 0, + aml_active_low = 1, +} AmlActiveHighAndLow; + +/* + * ACPI 1.0b: Table 6-28 Extended Interrupt Descriptor Definition + * _SHR field definition + */ +typedef enum { + aml_exclusive = 0, + aml_shared = 1, +} AmlExclusiveAndShared; + +/* + * ACPI 5.1: Table 6-203 Extended Interrupt Descriptor Definition + * _WKC field definition + */ +typedef enum { + aml_not_wake_capable = 0, + aml_wake_capable = 1, +} AmlWakeCap; + typedef struct AcpiBuildTables { GArray *table_data; @@ -170,6 +215,11 @@ Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3); Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4); Aml *aml_memory32_fixed(uint32_t addr, uint32_t size, AmlReadAndWrite read_and_write); +Aml *aml_interrupt(AmlConsumerAndProducer con_and_pro, + AmlLevelAndEdge level_and_edge, + AmlActiveHighAndLow high_and_low, + AmlExclusiveAndShared exclusive_and_shared, + AmlWakeCap wake_capable, uint32_t irq); Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base, uint8_t aln, uint8_t len); Aml *aml_operation_region(const char *name, AmlRegionSpace rs,