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[2a00:1450:400c:c09::22b]) by mx.google.com with ESMTPS id 2si6725216wmr.64.2016.02.18.09.45.56 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 18 Feb 2016 09:45:56 -0800 (PST) Received-SPF: pass (google.com: domain of eric.auger@linaro.org designates 2a00:1450:400c:c09::22b as permitted sender) client-ip=2a00:1450:400c:c09::22b; Authentication-Results: mx.google.com; spf=pass (google.com: domain of eric.auger@linaro.org designates 2a00:1450:400c:c09::22b as permitted sender) smtp.mailfrom=eric.auger@linaro.org; dkim=pass header.i=@linaro.org Received: by mail-wm0-x22b.google.com with SMTP id a4so36644567wme.1 for ; Thu, 18 Feb 2016 09:45:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=2qXCg2jgKQle8ICuFFR4Qf3Xp/liywVsUEm3WNnmO9A=; b=K5PFYmY7oSM3XKp/b29z/vgvRmuD64LSj2XaGzfdU5VeISZriaeA2kaet/g8qFe9IZ PrYCSj//88yWf5SI+iBV2LRJgQHiNFqviSgwWmNXOOnmUIJVQIYGz5VgEaRzBMIGdPQ1 l6VZGvJ1i30xZ/aVylRf034JTT66c75faHpn0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-type:content-transfer-encoding; bh=2qXCg2jgKQle8ICuFFR4Qf3Xp/liywVsUEm3WNnmO9A=; b=G0lKaGrtJTg8IJJ9WSF59TnmTTYfV9rtjOMwYogkZ4+d2DqL5eXgbYcudWKjnrURHn +Ht+b7qnv4txxB35Z+QrbAEeLqsDkabtJul5oGKb46/5S1KNjkwNBb+03piuRe2hwufU ExzQMUCFnXSHDgPQAgWTvev6uNJaC31QUKkK5VStJoXLJpy2rmUQ8SU4q62ix6SiPUj/ Rb+ssfTEf7eX1haDd3bw2u+xykyAwMhMu1l6uGHXmmJurgduv74IoKOpp+b0AKLagG3V 3w9xxEGge9FivrW+8LkIGKldjLfgtzGRKfvLNPck1gO88U9JM533qFJ/W+5TX5rVRU+W JLhA== X-Gm-Message-State: AG10YOQHEHAIH7KO97RilvU9PyyCmXvWxA3/mvpGcLZaD3SjypfrgPKFiN6kHPG6epnj92oGsKU= X-Received: by 10.194.250.35 with SMTP id yz3mr9706956wjc.173.1455817556610; Thu, 18 Feb 2016 09:45:56 -0800 (PST) Return-Path: Received: from midway01-04-00.lavalab ([81.128.185.50]) by smtp.gmail.com with ESMTPSA id ct2sm7592997wjb.46.2016.02.18.09.45.54 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 Feb 2016 09:45:54 -0800 (PST) From: Eric Auger To: eric.auger@st.com, eric.auger@linaro.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, alex.williamson@redhat.com, david@gibson.dropbear.id.au Cc: christoffer.dall@linaro.org, suravee.suthikulpanit@amd.com, alex.bennee@linaro.org, thuth@redhat.com, crosthwaitepeter@gmail.com, patches@linaro.org, pbonzini@redhat.com, b.reynal@virtualopensystems.com, thomas.lendacky@amd.com Subject: [PATCH v7 1/8] hw/vfio/platform: amd-xgbe device Date: Thu, 18 Feb 2016 17:45:39 +0000 Message-Id: <1455817546-6564-2-git-send-email-eric.auger@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1455817546-6564-1-git-send-email-eric.auger@linaro.org> References: <1455817546-6564-1-git-send-email-eric.auger@linaro.org> MIME-Version: 1.0 This patch introduces the amd-xgbe VFIO platform device. It allows the guest to do passthrough on a device exposing an "amd,xgbe-seattle-v1a" compat string. Signed-off-by: Eric Auger Reviewed-by: Alex Bennée --- RFC -> v1: - add Alex' R-b --- hw/vfio/Makefile.objs | 1 + hw/vfio/amd-xgbe.c | 55 +++++++++++++++++++++++++++++++++++++++++ include/hw/vfio/vfio-amd-xgbe.h | 51 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 107 insertions(+) create mode 100644 hw/vfio/amd-xgbe.c create mode 100644 include/hw/vfio/vfio-amd-xgbe.h -- 1.8.3.2 diff --git a/hw/vfio/Makefile.objs b/hw/vfio/Makefile.objs index d324863..ceddbb8 100644 --- a/hw/vfio/Makefile.objs +++ b/hw/vfio/Makefile.objs @@ -3,4 +3,5 @@ obj-$(CONFIG_SOFTMMU) += common.o obj-$(CONFIG_PCI) += pci.o pci-quirks.o obj-$(CONFIG_SOFTMMU) += platform.o obj-$(CONFIG_SOFTMMU) += calxeda-xgmac.o +obj-$(CONFIG_SOFTMMU) += amd-xgbe.o endif diff --git a/hw/vfio/amd-xgbe.c b/hw/vfio/amd-xgbe.c new file mode 100644 index 0000000..53451eb --- /dev/null +++ b/hw/vfio/amd-xgbe.c @@ -0,0 +1,55 @@ +/* + * AMD XGBE VFIO device + * + * Copyright Linaro Limited, 2015 + * + * Authors: + * Eric Auger + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + * + */ + +#include "hw/vfio/vfio-amd-xgbe.h" + +static void amd_xgbe_realize(DeviceState *dev, Error **errp) +{ + VFIOPlatformDevice *vdev = VFIO_PLATFORM_DEVICE(dev); + VFIOAmdXgbeDeviceClass *k = VFIO_AMD_XGBE_DEVICE_GET_CLASS(dev); + + vdev->compat = g_strdup("amd,xgbe-seattle-v1a"); + + k->parent_realize(dev, errp); +} + +static const VMStateDescription vfio_platform_amd_xgbe_vmstate = { + .name = TYPE_VFIO_AMD_XGBE, + .unmigratable = 1, +}; + +static void vfio_amd_xgbe_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + VFIOAmdXgbeDeviceClass *vcxc = + VFIO_AMD_XGBE_DEVICE_CLASS(klass); + vcxc->parent_realize = dc->realize; + dc->realize = amd_xgbe_realize; + dc->desc = "VFIO AMD XGBE"; + dc->vmsd = &vfio_platform_amd_xgbe_vmstate; +} + +static const TypeInfo vfio_amd_xgbe_dev_info = { + .name = TYPE_VFIO_AMD_XGBE, + .parent = TYPE_VFIO_PLATFORM, + .instance_size = sizeof(VFIOAmdXgbeDevice), + .class_init = vfio_amd_xgbe_class_init, + .class_size = sizeof(VFIOAmdXgbeDeviceClass), +}; + +static void register_amd_xgbe_dev_type(void) +{ + type_register_static(&vfio_amd_xgbe_dev_info); +} + +type_init(register_amd_xgbe_dev_type) diff --git a/include/hw/vfio/vfio-amd-xgbe.h b/include/hw/vfio/vfio-amd-xgbe.h new file mode 100644 index 0000000..9fff65e --- /dev/null +++ b/include/hw/vfio/vfio-amd-xgbe.h @@ -0,0 +1,51 @@ +/* + * VFIO AMD XGBE device + * + * Copyright Linaro Limited, 2015 + * + * Authors: + * Eric Auger + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + * + */ + +#ifndef HW_VFIO_VFIO_AMD_XGBE_H +#define HW_VFIO_VFIO_AMD_XGBE_H + +#include "hw/vfio/vfio-platform.h" + +#define TYPE_VFIO_AMD_XGBE "vfio-amd-xgbe" + +/** + * This device exposes: + * - 5 MMIO regions: MAC, PCS, SerDes Rx/Tx regs, + SerDes Integration Registers 1/2 & 2/2 + * - 2 level sensitive IRQs and optional DMA channel IRQs + */ +struct VFIOAmdXgbeDevice { + VFIOPlatformDevice vdev; +}; + +typedef struct VFIOAmdXgbeDevice VFIOAmdXgbeDevice; + +struct VFIOAmdXgbeDeviceClass { + /*< private >*/ + VFIOPlatformDeviceClass parent_class; + /*< public >*/ + DeviceRealize parent_realize; +}; + +typedef struct VFIOAmdXgbeDeviceClass VFIOAmdXgbeDeviceClass; + +#define VFIO_AMD_XGBE_DEVICE(obj) \ + OBJECT_CHECK(VFIOAmdXgbeDevice, (obj), TYPE_VFIO_AMD_XGBE) +#define VFIO_AMD_XGBE_DEVICE_CLASS(klass) \ + OBJECT_CLASS_CHECK(VFIOAmdXgbeDeviceClass, (klass), \ + TYPE_VFIO_AMD_XGBE) +#define VFIO_AMD_XGBE_DEVICE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(VFIOAmdXgbeDeviceClass, (obj), \ + TYPE_VFIO_AMD_XGBE) + +#endif