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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id g35si7738845qgf.43.2016.05.16.01.03.26 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 16 May 2016 01:03:26 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:43004 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b2DUs-0004jV-1x for patch@linaro.org; Mon, 16 May 2016 04:03:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52657) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b2DPT-00059e-M0 for qemu-devel@nongnu.org; Mon, 16 May 2016 03:57:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b2DPN-0000IX-Sa for qemu-devel@nongnu.org; Mon, 16 May 2016 03:57:50 -0400 Received: from mx1.redhat.com ([209.132.183.28]:40551) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b2DPE-0000EK-Tx; Mon, 16 May 2016 03:57:37 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 64872C05B1E1; Mon, 16 May 2016 07:57:36 +0000 (UTC) Received: from hawk.localdomain.com (ovpn-204-50.brq.redhat.com [10.40.204.50]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u4G7vPBH018488; Mon, 16 May 2016 03:57:33 -0400 From: Andrew Jones To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, qemu-devel@nongnu.org, qemu-arm@nongnu.org, andre.przywara@arm.com, peter.maydell@linaro.org, alex.bennee@linaro.org Date: Mon, 16 May 2016 09:57:17 +0200 Message-Id: <1463385444-12916-4-git-send-email-drjones@redhat.com> In-Reply-To: <1463385444-12916-1-git-send-email-drjones@redhat.com> References: <1463385444-12916-1-git-send-email-drjones@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Mon, 16 May 2016 07:57:36 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [kvm-unit-tests PATCH 03/10] arm/arm64: smp: support more than 8 cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marc.zyngier@arm.com, christoffer.dall@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Andrew Jones --- arm/run | 19 ++++++++++++------- arm/selftest.c | 5 ++++- lib/arm/asm/processor.h | 9 +++++++-- lib/arm/asm/setup.h | 4 ++-- lib/arm/setup.c | 12 +++++++++++- lib/arm64/asm/processor.h | 9 +++++++-- 6 files changed, 43 insertions(+), 15 deletions(-) -- 2.4.11 diff --git a/arm/run b/arm/run index ebf703d5757c7..119bd1eee3651 100755 --- a/arm/run +++ b/arm/run @@ -31,13 +31,6 @@ if [ -z "$ACCEL" ]; then fi fi -if [ "$HOST" = "aarch64" ] && [ "$ACCEL" = "kvm" ]; then - processor="host" - if [ "$ARCH" = "arm" ]; then - processor+=",aarch64=off" - fi -fi - qemu="${QEMU:-qemu-system-$ARCH_NAME}" qpath=$(which $qemu 2>/dev/null) @@ -53,6 +46,18 @@ fi M='-machine virt' +if [ "$ACCEL" = "kvm" ]; then + if $qemu $M,\? 2>&1 | grep gic-version > /dev/null; then + M+=',gic-version=host' + fi + if [ "$HOST" = "aarch64" ]; then + processor="host" + if [ "$ARCH" = "arm" ]; then + processor+=",aarch64=off" + fi + fi +fi + if ! $qemu $M -device '?' 2>&1 | grep virtconsole > /dev/null; then echo "$qpath doesn't support virtio-console for chr-testdev. Exiting." exit 2 diff --git a/arm/selftest.c b/arm/selftest.c index 75dc91faab69a..6c97900daf532 100644 --- a/arm/selftest.c +++ b/arm/selftest.c @@ -313,9 +313,10 @@ static bool psci_check(void) static cpumask_t smp_reported; static void cpu_report(void) { + unsigned long mpidr = get_mpidr(); int cpu = smp_processor_id(); - report("CPU%d online", true, cpu); + report("CPU(%3d) mpidr=%lx", mpidr_to_cpu(mpidr) == cpu, cpu, mpidr); cpumask_set_cpu(cpu, &smp_reported); halt(); } @@ -344,6 +345,7 @@ int main(int argc, char **argv) } else if (strcmp(argv[0], "smp") == 0) { + unsigned long mpidr = get_mpidr(); int cpu; report("PSCI version", psci_check()); @@ -354,6 +356,7 @@ int main(int argc, char **argv) smp_boot_secondary(cpu, cpu_report); } + report("CPU(%3d) mpidr=%lx", mpidr_to_cpu(mpidr) == 0, 0, mpidr); cpumask_set_cpu(0, &smp_reported); while (!cpumask_full(&smp_reported)) cpu_relax(); diff --git a/lib/arm/asm/processor.h b/lib/arm/asm/processor.h index f25e7eee3666c..d2048f5f5f7e6 100644 --- a/lib/arm/asm/processor.h +++ b/lib/arm/asm/processor.h @@ -40,8 +40,13 @@ static inline unsigned int get_mpidr(void) return mpidr; } -/* Only support Aff0 for now, up to 4 cpus */ -#define mpidr_to_cpu(mpidr) ((int)((mpidr) & 0xff)) +#define MPIDR_HWID_BITMASK 0xffffff +extern int mpidr_to_cpu(unsigned long mpidr); + +#define MPIDR_LEVEL_SHIFT(level) \ + (((1 << level) >> 1) << 3) +#define MPIDR_AFFINITY_LEVEL(mpidr, level) \ + ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & 0xff) extern void start_usr(void (*func)(void *arg), void *arg, unsigned long sp_usr); extern bool is_user(void); diff --git a/lib/arm/asm/setup.h b/lib/arm/asm/setup.h index cb8fdbd38dd5d..c501c6ddd8657 100644 --- a/lib/arm/asm/setup.h +++ b/lib/arm/asm/setup.h @@ -10,8 +10,8 @@ #include #include -#define NR_CPUS 8 -extern u32 cpus[NR_CPUS]; +#define NR_CPUS 255 +extern u64 cpus[NR_CPUS]; extern int nr_cpus; #define NR_MEM_REGIONS 8 diff --git a/lib/arm/setup.c b/lib/arm/setup.c index 8c6172ff94106..1d6b6949c920e 100644 --- a/lib/arm/setup.c +++ b/lib/arm/setup.c @@ -24,12 +24,22 @@ extern unsigned long stacktop; extern void io_init(void); extern void setup_args(const char *args); -u32 cpus[NR_CPUS] = { [0 ... NR_CPUS-1] = (~0U) }; +u64 cpus[NR_CPUS] = { [0 ... NR_CPUS-1] = (~0U) }; int nr_cpus; struct mem_region mem_regions[NR_MEM_REGIONS]; phys_addr_t __phys_offset, __phys_end; +int mpidr_to_cpu(unsigned long mpidr) +{ + int i; + + for (i = 0; i < nr_cpus; ++i) + if (cpus[i] == (mpidr & MPIDR_HWID_BITMASK)) + return i; + return -1; +} + static void cpu_set(int fdtnode __unused, u32 regval, void *info __unused) { int cpu = nr_cpus++; diff --git a/lib/arm64/asm/processor.h b/lib/arm64/asm/processor.h index 9a208ff729b7e..7e448dc81a6aa 100644 --- a/lib/arm64/asm/processor.h +++ b/lib/arm64/asm/processor.h @@ -78,8 +78,13 @@ static inline type get_##reg(void) \ DEFINE_GET_SYSREG64(mpidr) -/* Only support Aff0 for now, gicv2 only */ -#define mpidr_to_cpu(mpidr) ((int)((mpidr) & 0xff)) +#define MPIDR_HWID_BITMASK 0xff00ffffff +extern int mpidr_to_cpu(unsigned long mpidr); + +#define MPIDR_LEVEL_SHIFT(level) \ + (((1 << level) >> 1) << 3) +#define MPIDR_AFFINITY_LEVEL(mpidr, level) \ + ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & 0xff) extern void start_usr(void (*func)(void *arg), void *arg, unsigned long sp_usr); extern bool is_user(void);