From patchwork Tue Jun 14 14:38:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 70008 Delivered-To: patches@linaro.org Received: by 10.140.106.246 with SMTP id e109csp2084202qgf; Tue, 14 Jun 2016 07:38:40 -0700 (PDT) X-Received: by 10.194.94.165 with SMTP id dd5mr6591970wjb.31.1465915120809; Tue, 14 Jun 2016 07:38:40 -0700 (PDT) Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id c11si4451355wmi.99.2016.06.14.07.38.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Jun 2016 07:38:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1bCpUB-0006Kf-Cs; Tue, 14 Jun 2016 15:38:35 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Shlomo Pongratz , Shlomo Pongratz , Pavel Fedin , Shannon Zhao , Christoffer Dall Subject: [PATCH v3 04/20] target-arm: Provide hook to tell GICv3 about changes of security state Date: Tue, 14 Jun 2016 15:38:16 +0100 Message-Id: <1465915112-29272-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1465915112-29272-1-git-send-email-peter.maydell@linaro.org> References: <1465915112-29272-1-git-send-email-peter.maydell@linaro.org> The GICv3 CPU interface needs to know when the CPU it is attached to makes an exception level or mode transition that changes the security state, because whether it is asserting IRQ or FIQ can change depending on these things. Provide a mechanism for letting the GICv3 device register a hook to be called on such changes. Signed-off-by: Peter Maydell Reviewed-by: Shannon Zhao --- target-arm/cpu.c | 9 +++++++++ target-arm/cpu.h | 34 ++++++++++++++++++++++++++++++++++ target-arm/helper.c | 2 ++ target-arm/internals.h | 8 ++++++++ target-arm/op_helper.c | 4 ++++ 5 files changed, 57 insertions(+) -- 1.9.1 diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 3fd0743..0eaa907 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -51,6 +51,15 @@ static bool arm_cpu_has_work(CPUState *cs) | CPU_INTERRUPT_EXITTB); } +void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, + void *opaque) +{ + /* We currently only support registering a single hook function */ + assert(!cpu->el_change_hook); + cpu->el_change_hook = hook; + cpu->el_change_hook_opaque = opaque; +} + static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) { /* Reset a single ARMCPRegInfo register */ diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 2c2b8f7..1c06090 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -515,6 +515,13 @@ typedef struct CPUARMState { } CPUARMState; /** + * ARMELChangeHook: + * type of a function which can be registered via arm_register_el_change_hook() + * to get callbacks when the CPU changes its exception level or mode. + */ +typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque); + +/** * ARMCPU: * @env: #CPUARMState * @@ -652,6 +659,9 @@ struct ARMCPU { /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ uint32_t dcz_blocksize; uint64_t rvbar; + + ARMELChangeHook *el_change_hook; + void *el_change_hook_opaque; }; static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) @@ -2384,4 +2394,28 @@ static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) } #endif +/** + * arm_register_el_change_hook: + * Register a hook function which will be called back whenever this + * CPU changes exception level or mode. The hook function will be + * passed a pointer to the ARMCPU and the opaque data pointer passed + * to this function when the hook was registered. + * + * Note that we currently only support registering a single hook function, + * and will assert if this function is called twice. + * This facility is intended for the use of the GICv3 emulation. + */ +void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, + void *opaque); + +/** + * arm_get_el_change_hook_opaque: + * Return the opaque data that will be used by the el_change_hook + * for this CPU. + */ +static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu) +{ + return cpu->el_change_hook_opaque; +} + #endif diff --git a/target-arm/helper.c b/target-arm/helper.c index 862e780..2ea210e 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -6500,6 +6500,8 @@ void arm_cpu_do_interrupt(CPUState *cs) arm_cpu_do_interrupt_aarch32(cs); } + arm_call_el_change_hook(cpu); + if (!kvm_enabled()) { cs->interrupt_request |= CPU_INTERRUPT_EXITTB; } diff --git a/target-arm/internals.h b/target-arm/internals.h index 728ecba..466be0b 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -479,4 +479,12 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write, int is_user, uintptr_t retaddr); +/* Call the EL change hook if one has been registered */ +static inline void arm_call_el_change_hook(ARMCPU *cpu) +{ + if (cpu->el_change_hook) { + cpu->el_change_hook(cpu, cpu->el_change_hook_opaque); + } +} + #endif diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 35912a1..73da759 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -474,6 +474,8 @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) { cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn); + + arm_call_el_change_hook(arm_env_get_cpu(env)); } /* Access to user mode registers from privileged modes. */ @@ -969,6 +971,8 @@ void HELPER(exception_return)(CPUARMState *env) env->pc = env->elr_el[cur_el]; } + arm_call_el_change_hook(arm_env_get_cpu(env)); + return; illegal_return: